Rafael Peset Llopis

发表

Short destabilizing paths in timing verification

Jordi Carrabina, Rafael Peset Llopis, Lluis Ribas, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A low-cost and low-power multi-standard video encoder

Rafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

Kees G. W. Goossens, Om Prakash Gangwal, Rafael Peset Llopis, 2002, Des. Autom. Embed. Syst..

Low-cost and real-time super-resolution over a video encoder IP

Gustavo Marrero Callicó, Antonio Núñez, Rafael Peset Llopis, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Impact of shared data in MPEG-4 H.264/AVC parallelisation

Lambert Spaanenburg, Rafael Peset Llopis, C Wang, 2007 .

Low-Cost Super-Resolution Algorithms Implementation Over a HW/SW Video Compression Platform

Sebastián López, Gustavo Marrero Callicó, José Francisco López, 2006, EURASIP J. Adv. Signal Process..

Path sensitization of combinational circuits and its impact on clocking of sequential systems

Rafael Peset Llopis, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

HW-SW co-design and verification of a multi-standard video and image codec

Jim Lin, Rafael Peset Llopis, Ramanathan Sethuraman, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Low power, testable dual edge triggered flip-flops

Manoj Sachdev, Rafael Peset Llopis, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

A combined pairing and chaining algorithm for CMOS layout generation

Jordi Carrabina, Rafael Peset Llopis, Xavier Marin, 1996, Proceedings ED&TC European Design and Test Conference.

Networks on Chips for High-End Consumer-Electronics TV System Architectures

Kees G. W. Goossens, Björn Nilsson, Rafael Peset Llopis, 2006, Proceedings of the Design Automation & Test in Europe Conference.

High-Level Power Estimation Methodology Applied for Processor-Level DTSE

Rafael Peset Llopis, Jos Huisken, P. E. R. Lippens, 2000 .

Exact path sensitization in timing analysis

Rafael Peset Llopis, 1994, EURO-DAC '94.

RAPIDO: a modular, multi-board, heterogeneous multi-processor, PCI bus based prototyping framework for the validation of SoC VLSI designs

Rafael Peset Llopis, Natalino G. Busá, Ghiath Alkadi, 2002, Proceedings 13th IEEE International Workshop on Rapid System Prototyping.

High Level Power Estimation

Rafael Peset Llopis, 1997, DAC 1997.

The Petrol approach to high-level power estimation

Kees G. W. Goossens, Rafael Peset Llopis, K. Goossens, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

A fast and accurate characterization method for full-CMOS circuits

Hans G. Kerkhoff, Rafael Peset Llopis, H. Kerkhoff, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Segment-based motion estimation using a block-based engine

Rafael Peset Llopis, Ramanathan Sethuraman, Fabian Ernst, 2005, 2005 13th European Signal Processing Conference.