Tien-Sheng Chao

发表

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

Tiao-Yuan Huang, Yao-Jen Lee, Tien-Sheng Chao, 2005, Microelectron. Reliab..

Novel Bi-directional tunneling program/erase NOR (BiNOR) type flash EEPROM

Evans Ching-Song Yang, Tien-Sheng Chao, Cheng-Jye Liu, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Mix-and-match lithography processes for 0.1-um MOS transistor device fabrication

Horng-Chih Lin, Tien-Sheng Chao, Kazumitsu Nakamura, 1996, Advanced Lithography.

A domain partition approach to parallel adaptive simulation of dynamic threshold voltage MOSFET

Yiming Li, Tien-Sheng Chao, S. M. Sze, 2002 .

Mix-and-match lithography technology on 6-in. wafers for nanofabrication

Shyi-Long Shy, Tan Fu Lei, Wen-an Loong, 1995, Photomask Technology.

High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method

Chien-Hung Chen, Tien-Sheng Chao, Chien-Hsing Lee, 2009, IEEE Electron Device Letters.

Parallel Dynamic Partition and Adaptive Computation in Semiconductor Device Simulation

Yiming Li, Tien-Sheng Chao, S. M. Sze, 2001, PPSC.

A new parallel adaptive finite volume method for the numerical simulation of semiconductor devices

Tien-Sheng Chao, S. M. Sze, Jinn-Liang Liu, 2001 .

A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation

Yiming Li, Tien-Sheng Chao, S. M. Sze, 2002, Engineering with Computers.

NH3 Plasma Treatment for Flash Memory on Poly-Si Thin Films

Yu-Hsien Lin, Tien-Sheng Chao, Hsin-Chiang You, 2012, 2012 International Symposium on Computer, Consumer and Control.

Conducting poly(aniline-co-N-propanesulfonic acid aniline) (PAPSAH) as charge dissipation layer for e-beam lithography

Shyi-Long Shy, Tan Fu Lei, Chun-Yen Chang, 1996, Photomask Technology.

High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in nor-Type Flash Memory

Chien-Hung Chen, Tien-Sheng Chao, Chien-Hsing Lee, 2010, IEEE Transactions on Electron Devices.

High quality ultra-thin (2.4 nm) oxide prepared by clustered vertical furnace with in-situ HF-vapor pre-gate oxide cleaning

Tien-Sheng Chao, Chao-Sung Lai, T. Y. Huang, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration

Tien-Sheng Chao, Kuan-Ti Wang, Wan-Chyi Lin, 2010, IEEE Electron Device Letters.

High-frequency characteristics of PMOS transistors with raised SiGe source/drain

Guo-Wei Huang, Chun-Yen Chang, Tien-Sheng Chao, 2001, 2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers (IEEE Cat. No.01EX496).

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

Horng-Chih Lin, Tiao-Yuan Huang, Tien-Sheng Chao, 2010, Microelectron. Reliab..

Improvement in pH Sensitivity of Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Sensors Using H2 Sintering

Tien-Sheng Chao, Fang-Yu Chang, Tung-Ming Pan, 2014, Sensors.

Parallel dynamic load balancing for semiconductor device simulations on a linux cluster

Shao-Ming Yu, Tien-Sheng Chao, S. M. Sze, 2001 .

Novel 2-Bit/Cell Wrapped-Select-Gate SONOS TFT Memory Using Source-Side Injection for NOR-Type Flash Array

Tien-Sheng Chao, Chia-Chun Liao, Kuan-Ti Wang, 2012 .

High-Performance HfO2 Gate Dielectrics Fluorinated by Postdeposition CF4 Plasma Treatment

Tien-Sheng Chao, Chao-Sung Lai, Jer-Chyi Wang, 2007 .

AHighly Reliable Multi-level and2-bit/cell Operation ofWrapped-Select-Gate (WSG)SONOS

Chih-Hung Lin, Chien-Hung Chen, Tien-Sheng Chao, 2007 .

High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices

Tan Fu Lei, Tien-Sheng Chao, Tung-Ming Pan, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

The Effects of Dielectric Type and Thickness on the Characteristics of Dynamic Threshold Metal Oxide Semiconductor Transistors

Tiao-Yuan Huang, Tien-Sheng Chao, Yao-Jen Lee, 2003 .

High performance 0.1 /spl mu/m dynamic threshold MOSFET using indium channel implantation

Tiao-Yuan Huang, Chun-Yen Chang, Tien-Sheng Chao, 2000 .

New insights into breakdown modes and their evolution in ultra-thin gate oxide

Tiao-Yuan Huang, Tien-Sheng Chao, Da-Yuan Lee, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

Tien-Sheng Chao, Chao-Sung Lai, Wen-Luh Yang, 2007, IEEE Electron Device Letters.

Thin polyoxide on the top of poly-Si gate to suppress boron penetration for pMOS

Tan Fu Lei, Tien-Sheng Chao, T. Chao, 1995 .

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Horng-Chih Lin, Tiao-Yuan Huang, Chun-Yen Chang, 2000 .

Fourier Transform Infrared Spectroscopic Study of Oxide Films Grown in Pure N2O

Tan Fu Lei, Tien-Sheng Chao, T. Chao, 1995 .

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

Tiao-Yuan Huang, Chun-Yen Chang, Tien-Sheng Chao, 2000 .

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Guo-Wei Huang, Tuo-Hung Hou, Tien-Sheng Chao, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Suppression of boron penetration by using inductive-coupling-nitrogen-plasma in stacked amorphous/polysilicon gate structure

Tan Fu Lei, Don-Gey Liu, Tien-Sheng Chao, 1997 .

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Horng-Chih Lin, Tien-Sheng Chao, Tzu-I Tsai, 2011, IEEE Electron Device Letters.

Suppression of boron penetration in p+-poly-Si gate metal-oxide-semiconductor transistor using nitrogen implantation

Tan Fu Lei, Tien-Sheng Chao, Chao-Hsin Chien, 1997 .

A novel shallow trench isolation technique

Tan Fu Lei, Tien-Sheng Chao, Juing–Yi Cheng, 1997 .

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Tien-Sheng Chao, Chao-Sung Lai, Wen-Luh Yang, 2008 .

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Tien-Sheng Chao, Chia-Chun Liao, Wen-Luh Yang, 2010, IEEE Transactions on Electron Devices.

Post-polysilicon gate-proces-induced degradation on thin gate oxide

Tan Fu Lei, Tien-Sheng Chao, Chao-Sung Lai, 1995 .

Trapping/detrapping characteristics of electrons and holes under dynamic NBTI stress on HfO2 and HfSiON gate dielectrics

Tien-Sheng Chao, Jen-Chung Lou, Yao-Jen Lee, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Impact of High-$\kappa$ Offset Spacer in 65-nm Node SOI Devices

Chien-Hung Wu, Tien-Sheng Chao, Shui-Jinn Wang, 2007, IEEE Electron Device Letters.

Reduced reverse narrow channel effect in thin SOI nMOSFETs

Tiao-Yuan Huang, Chun-Yen Chang, Tien-Sheng Chao, 2000 .

Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films

Tan Fu Lei, Tien-Sheng Chao, Chao-Sung Lai, 1998 .

Nanometer-scale conversion of Si3N4 to SiOx

Tien-Sheng Chao, Wen-Feng Hsieh, J.-W. Chang, 2000 .

Label-free and real-time detection of ferritin using a horn-like polycrystalline-silicon nanowire field-effect transistor biosensor

Tien-Sheng Chao, Tung-Ming Pan, Li-Chen Yen, 2016 .

Suppression of interfacial reaction for HfO2 on silicon by pre-CF4 plasma treatment

Tien-Sheng Chao, Chao-Sung Lai, Li-Lin Tay, 2006 .