Paul V. Gratz

发表

Synchronized progress in interconnection networks (SPIN), a new approach to address deadlocks

Paul V. Gratz, 2019 .

DRAIN: Deadlock Removal for Arbitrary Irregular Networks

Natalie D. Enright Jerger, Tushar Krishna, Joshua San Miguel, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom

Tushar Krishna, Paul V. Gratz, Aniruddh Ramrakhyani, 2019, IEEE Micro.

MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors

Daniel A. Jiménez, Paul V. Gratz, Laith M. AlBarakat, 2018, IEEE Computer Architecture Letters.

The TRIPS OPN: A Processor Integrated NoC for Operand Bypass

Stephen W. Keckler, Paul V. Gratz, 2010 .

vNVML: An Efficient User Space Library for Virtualizing and Sharing Non-Volatile Memories

Doug Voigt, Paul V. Gratz, Chih Chieh Chou, 2019, 2019 35th Symposium on Mass Storage Systems and Technologies (MSST).

SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors

Daniel A. Jiménez, Paul V. Gratz, Daniel A. Jiménez, 2020, ICS.

FPGA-based Hyrbid Memory Emulation System pdf

Fei Wen, Paul V. Gratz, Mian Qin, 2020, ArXiv.

Realistic Workload Characterization and Analysis for Networks-on-Chip Design

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2009 .

Virtualize and share non-volatile memories in user space

A. L. Narasimha Reddy, Doug Voigt, Paul V. Gratz, 2020, CCF Trans. High Perform. Comput..

A Generic FPGA Accelerator for Minimum Storage Regenerating Codes

Rekha Pitchumani, Joo Hwan Lee, Paul V. Gratz, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution

Joshua San Miguel, Mayank Parasar, Paul V. Gratz, 2019, MICRO.

Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors

Cheng Li, Samuel Palermo, Paul V. Gratz, 2015 .

An Evaluation of the TRIPS Computer System (Extended Technical Report)

Kathryn S. McKinley, Bertrand A. Maher, Mario Donato Marino, 2008 .

Network-on-chip implementation and performance improvement through workload characterization and congestion awareness

Stephen W. Keckler, Paul V. Gratz, S. Keckler, 2008 .

Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs

Paul V. Gratz, Ahmad M. Radaideh, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Architecture And Implementation Of The Trips Processor

Simha Sethumadhavan, Karthikeyan Sankaralingam, Stephen W. Keckler, 2007 .

SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing

Yoon Seok Yang, Hrishikesh Deshpande, Paul V. Gratz, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip

Cheng Li, Samuel Palermo, Paul V. Gratz, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Ocin_tsim: a DVFS-aware simulator for NoC based platforms.

Boris Grot, Paul V. Gratz, S Prabhu, 2009 .

KVRAID: high performance, write efficient, update friendly erasure coding scheme for KV-SSDs

Rekha Pitchumani, A. L. Narasimha Reddy, Paul V. Gratz, 2021, SYSTOR.

SEEC: stochastic escape express channel

Tushar Krishna, Joshua San Miguel, Mayank Parasar, 2021, SC.

Pitstop: Enabling a Virtual Network Free Network-on-Chip

Natalie D. Enright Jerger, Tushar Krishna, Joshua San Miguel, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Ocin tsim-DVFS Aware Simulator for NoCs

Paul V. Gratz, S. Prabhu, Boris Grot, 2009 .

AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation

Paul Gratz, Paul V. Gratz, Swapnil Lotlikar, 2011, 2011 24th Internatioal Conference on VLSI Design.

Asynchronous Bypass Channel Routers

Paul V. Gratz, A. Sprintson, Tushar N. K. Jain, 2009 .

Lookahead Prefetching with Signature Path

Jinchun Kim, A. L. Narasimha Reddy, Paul V. Gratz, 2015 .

A BRANCH-DIRECTED DATA CACHE PREFETCHING TECHNIQUE FOR INORDER PROCESSORS

Paul V. Gratz, 2011 .

The Temporal Ancestry Prefetcher

Daniel A. Jiménez, Paul V. Gratz, D. Jiménez, 2020 .

Reducing Minor Page Fault Overheads through Enhanced Page Walker

Paul V. Gratz, N. Reddy, Chandrahas Tirumalasetty, 2021, ACM Transactions on Architecture and Code Optimization.

Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems

Paul V. Gratz, O. Sinanoglu, Gino Chacon, 2022, IEEE Computer Architecture Letters.

The Championship Simulator: Architectural Simulation for Education and Competition

Seth H. Pugsley, Daniel A. Jiménez, Paul V. Gratz, 2022, ArXiv.

HMMU: A Hardware-based Hybrid Memory Management Unit

Paul V. Gratz, Fei Wen, Mian Qin, 2021 .

Automatic Microprocessor Performance Bug Detection pdf

Paul Gratz, Jiang Hu, Paul V. Gratz, 2020, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Use It or Lose It

Maria K. Michael, Stavros Hadjitheophanous, Paul Gratz, 2015, ACM Trans. Design Autom. Electr. Syst..

Perceptron-Based Prefetch Filtering

Seth H. Pugsley, Daniel A. Jiménez, Paul Gratz, 2019, 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA).

Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems

Paul V. Gratz, N. Reddy, Fei Wen, 2022, ACM Trans. Embed. Comput. Syst..

Bandwidth-efficient on-chip interconnect designs for GPGPUs

Jinchun Kim, Paul Gratz, Ki Hwan Yum, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

SpecLock: Speculative Lock Forwarding

George Michelogiannakis, Pooria M. Yaghini, Paul Gratz, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches

Xi Chen, Jiang Hu, Ümit Y. Ogras, 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end

Paul V. Gratz, D. Jiménez, Krishnendra Nathella, 2023, 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy

Jinchun Kim, Seth H. Pugsley, Chris Wilkerson, 2017, ASPLOS.

Path confidence based lookahead prefetching

Jinchun Kim, Seth H. Pugsley, Chris Wilkerson, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Coherence Attacks and Countermeasures in Interposer-Based Systems

Ozgur Sinanoglu, Paul Gratz, Johann Knechtel, 2021, 2105.02917.

Regional congestion awareness for load balance in networks-on-chip

Stephen W. Keckler, Paul Gratz, Boris Grot, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management

Xi Chen, Jiang Hu, Paul Gratz, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

ILP and TLP in shared memory applications: A limit study

Paul Gratz, Paul V. Gratz, Ehsan Fatehi, 2014, 2014 23rd International Conference on Parallel Architecture and Compilation (PACT).

Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom

Paul Gratz, Tushar Krishna, Paul V. Gratz, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Stochastic Pre-classification for SDN Data Plane Matching

Alexander Sprintson, Paul Gratz, Paul V. Gratz, 2014, 2014 IEEE 22nd International Conference on Network Protocols.

Stochastic Pre-Classification for Software Defined Firewalls

Alexander Sprintson, Paul Gratz, Paul V. Gratz, 2013, 2013 22nd International Conference on Computer Communication and Networks (ICCCN).

SIMD-Matcher: A SIMD-based Arbitrary Matching Framework

Paul V. Gratz, A. Sprintson, Fei Wen, 2022, ACM Trans. Archit. Code Optim..

Machine Learning for Microprocessor Performance Bug Localization

Paul V. Gratz, Erick Carvajal Barboza, M. Ketkar, 2023, ArXiv.

Dynamic Memory Pressure Aware Ballooning

Jinchun Kim, A. L. Narasimha Reddy, Paul Gratz, 2015, MEMSYS.

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors

Daniel A. Jiménez, Paul V. Gratz, Reena Panda, 2014, Micro.

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors

Reena Panda, Daniel A. Jiménez, Paul Gratz, 2012, IEEE Computer Architecture Letters.

SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches

Daniel A. Jiménez, Paul V. Gratz, Laith M. AlBarakat, 2022, 2022 IEEE 40th International Conference on Computer Design (ICCD).

Speculative paging for future NVM storage

Jinchun Kim, A. L. Narasimha Reddy, Paul Gratz, 2017, MEMSYS.

Interposer-Based Root of Trust pdf

Ozgur Sinanoglu, Paul Gratz, Johann Knechtel, 2021, ArXiv.

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Simha Sethumadhavan, Karthikeyan Sankaralingam, Doug Burger, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Implementation and Evaluation of On-Chip Network Architectures

Doug Burger, Stephen W. Keckler, Paul Gratz, 2006, 2006 International Conference on Computer Design.

LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip

Cheng Li, Samuel Palermo, Paul Gratz, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Xi Chen, Jiang Hu, Ümit Y. Ogras, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Page Size Aware Cache Prefetching

Daniel A. Jiménez, Paul V. Gratz, Lluc Alvarez, 2022, 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO).

Energy-efficient implementations of GF (p) and GF(2m) elliptic curve cryptography

Paul Gratz, Paul V. Gratz, Andrew D. Targhetta, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

The design space of ultra-low energy asymmetric cryptography

Paul Gratz, Paul V. Gratz, Andrew D. Targhetta, 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

Daniel A. Jiménez, Paul Gratz, Hyungjun Kim, 2014, IEEE Transactions on Computers.

Use It or Lose It

Paul V. Gratz, Siva Bhanu Krishna Boga, A. Vitkovskiy, 2015, ACM Trans. Design Autom. Electr. Syst..

Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory

Jiang Hu, Srinivas Shakkottai, Paul Gratz, 2016, TODE.

Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management

Jiang Hu, Srinivas Shakkottai, Paul Gratz, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Flow Correlator: A Flow Table Cache Management Strategy

Paul V. Gratz, A. Sprintson, Luke McHale, 2023, ArXiv.

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching

Daniel A. Jiménez, Paul V. Gratz, Elvira Teran, 2023, IEEE Computer Architecture Letters.