Kazuyoshi Nishimura

发表

1.25/10.3 Gbit/s dual-rate burst-mode receiver

Kazutaka Hara, Makoto Tsubokawa, Naoto Yoshimoto, 2008 .

High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system

Kazutoshi Kato, Youichi Fukada, Ken-Ichi Suzuki, 2007, IEICE Electron. Express.

13.9 A 10Gb/s Burst-Mode Adaptive Gain Select Limiting Amplifier in 0.13µm CMOS

Masafumi Nogawa, Kazuyoshi Nishimura, Tomoaki Kawamura, 2006 .

A 10.3125-Gbit/s SiGe BiCMOS Burst-Mode Clock and Data Recovery Circuit with 160-bit Consecutive Identical Digit Tolerance

Jun Terada, Kazuyoshi Nishimura, Tomoaki Kawamura, 2007 .

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

Tomoaki Yoshida, Masafumi Nogawa, Kazuyoshi Nishimura, 2008, IEICE Trans. Electron..

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion

Noboru Ishihara, Kazuyoshi Nishimura, Tomoaki Kawamura, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC

Jun Terada, Naoto Yoshimoto, Hiroaki Katsurai, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

a Jitter-Tolerant Parallel CDR

Hiroshi Koizumi, Masafumi Nogawa, Kazuyoshi Nishimura, 2004 .

Requirements for highly reliable VLSI multilevel interconnection

Kazuyoshi Nishimura, Yusuke Ohtomo, 1998 .

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Jun Terada, Naoto Yoshimoto, Hiroaki Katsurai, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI

Hiroshi Koizumi, Masafumi Nogawa, Kazuyoshi Nishimura, 2008, IEICE Trans. Electron..

A fast-response and high-sensitivity PIN-TIA module with wide dynamic range for 10 G burst-mode transmissions

Keiji Kishine, Kazuyoshi Nishimura, Makoto Nakamura, 2007 .

DC to 50 GHz single-pole four-throw InP-HEMT switch IC with highly uniform performance

Kazuyoshi Nishimura, Takatomo Enoki, Suehiro Sugitani, 2009 .

A 10.3125-Gbit/s SiGe BiCMOS Burst-Mode 3R Receiver for 10G-EPON Systems

Jun Terada, Keiji Kishine, Takamasa Imai, 2007, OFC 2007.

A 10-Gb/s burst-mode limiting amplifier using a two-stage active feedback circuit

Jun Terada, Masafumi Nogawa, Kazuyoshi Nishimura, 2009, 2009 Symposium on VLSI Circuits.

10.3 Gbit/s burst-mode PIN-TIA module with high sensitivity, wide dynamic range and quick response

Keiji Kishine, Kazuyoshi Nishimura, Shunji Kimura, 2008 .

High-speed circuit technology for 10-Gb/s optical burst-mode transmission

Masafumi Nogawa, Hiroaki Katsurai, Kazuyoshi Nishimura, 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.