Hans Jürgen Mattausch

发表

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction

Fengwei An, Xiangyu Zhang, Yuki Fujita, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign

Fengwei An, Hans Jürgen Mattausch, 2012, 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies.

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Hans Jürgen Mattausch, Tetsushi Koide, R. Kimura, 2010, 2010 First International Conference on Networking and Computing.

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

Hans Jürgen Mattausch, Kazutami Arimoto, Katsumi Dosaka, 2006, IEICE Trans. Electron..

Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design

Hans Jürgen Mattausch, Norio Sadachika, Shu Mimura, 2011, IEICE Trans. Electron..

Application of Multi-ported CAM for Parallel Coding

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2007, IEICE Trans. Inf. Syst..

Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions

Aiwen Luo, Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 2019, 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE).

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, IEICE Trans. Inf. Syst..

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh

Hans Jürgen Mattausch, Kazutami Arimoto, Kazuyasu Fujishima, 2005, IEICE Trans. Electron..

A scalable massively parallel processor for real-time image processing

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding

Hans Jürgen Mattausch, Akio Kawabata, Tetsushi Koide, 2010, 2010 First International Conference on Networking and Computing.

Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators

Lei Chen, Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Yasuhiro Okada, 2017, IEICE Trans. Electron..

Chip size and performance evaluations of shared cache for on-chip multiprocessor

Takahiro Sasaki, Tetsuo Hironaka, Hans Jürgen Mattausch, 2005, Systems and Computers in Japan.

Real-time hybrid learning and recognition system with software-hardware cooperation

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2011, 2011 IEEE International Conference on Robotics and Biomimetics.

Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters

Hans Jürgen Mattausch, Atsushi Saito, Mitiko Miura-Mattausch, 2016, IEICE Trans. Electron..

LVQ neural network SoC adaptable to different on-chip learning and recognition applications

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories

Hans Jürgen Mattausch, Yuki Tanaka, Ali Ahmadi, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A SoPC architecture for nearest-neighbor based learning and recognition

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, 2014 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Compact modeling approach for electro-mechanical system simulation

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Dondee Navarro, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

An associative memory-based learning model with an efficient hardware implementation in FPGA

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2011, Expert Syst. Appl..

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, N. Yorino, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems

Hans Jürgen Mattausch, Takeshi Kumaki, Tetsushi Koide, 2011, IEICE Trans. Inf. Syst..

Associative memory with fully parallel nearest-manhattan-distance search for low-power real-time single-chip applications

Hans Jürgen Mattausch, Tetsushi Koide, Yuji Yano, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2007, IEICE Trans. Inf. Syst..

Non-quasi-static carrier dynamics of MOSFETs under low-voltage operation

Hans Jürgen Mattausch, Toshiro Tsukada, Norio Sadachika, 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2008, IEICE Trans. Electron..

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words

Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, 2007, IEICE Trans. Electron..

Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions

Hans Jürgen Mattausch, Chenyue Ma, Mitiko Miura-Mattausch, 2013, IEICE Trans. Electron..

A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration

Fengwei An, Xiangyu Zhang, Lei Chen, 2016, IEEE Transactions on Multi-Scale Computing Systems.

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, N. Yorino, 2018, 2018 IEEE International Conference on Simulation, Modeling, and Programming for Autonomous Robots (SIMPAR).

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching

Fengwei An, Lei Chen, Hans Jürgen Mattausch, 2016, IEICE Trans. Electron..

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2005, IEICE Trans. Electron..

Memory-based hardware-accelerated system for high-speed human detection

Fengwei An, Hans Jürgen Mattausch, Indra Bagus Wicaksono, 2014, Adv. Robotics.

Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Masataka Miyake, 2014, IEICE Trans. Electron..

A parallel hardware design for parametric active contour models

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2005, IEEE Conference on Advanced Video and Signal Based Surveillance, 2005..

Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization

Hans Jürgen Mattausch, Takahiro Murakami, Norio Sadachika, 2008, IEICE Trans. Electron..

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline

Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA

Hans Jürgen Mattausch, Ali Ahmadi, Tetsushi Koide, 2006, 2006 IEEE International Conference on Evolutionary Computation.

Correlation method of circuit-performance and technology fluctuations for improved design reliability

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2001, ASP-DAC '01.

Compact modeling of dynamic trap density evolution for predicting circuit-performance aging

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, 2018, Microelectron. Reliab..

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, Asia and South Pacific Conference on Design Automation, 2006..

NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Dondee Navarro, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features

Hans Jürgen Mattausch, Kazutami Arimoto, Tetsushi Koide, 2005, IEICE Trans. Electron..

Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Takahiro Iizuka, 2019, IEICE Trans. Electron..

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping

Hans Jürgen Mattausch, Akio Kawabata, Tetsushi Koide, 2012, IEEE Journal of Solid-State Circuits.

Human recognition with a hardware-accelerated multi-prototype learning and classification system

Fengwei An, Hans Jürgen Mattausch, Indra Bagus Wicaksono, 2012, 2012 IEEE International Conference on Robotics and Biomimetics (ROBIO).

Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump

Lei Chen, Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation

Hans Jürgen Mattausch, Akihiro Tanaka, Mitiko Miura-Mattausch, 2013, IEICE Trans. Electron..

K-means clustering algorithm for multimedia applications with flexible HW/SW co-design

Fengwei An, Hans Jürgen Mattausch, 2013, J. Syst. Archit..

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, IEICE Trans. Inf. Syst..

A low-power video segmentation LSI with boundary-active-only architecture

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005, ASP-DAC.

Compact Modeling for Power Efficient Circuit Design

Hans Jürgen Mattausch, Atsushi Saito, Mitiko Miura-Mattausch, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors

Tetsuo Hironaka, Hans Jürgen Mattausch, Hiroshi Uchida, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

The Physics and Modeling of Mosfets - Surface-Potential Model HiSIM

Hans Jürgen Mattausch, Tatsuya Ezaki, Mitiko Miura-Mattausch, 2008, International Series on Advances in Solid State Electronics and Technology.

Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures

Fengwei An, Xiangyu Zhang, Lei Chen, 2017, Sensors.

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide, 2012, IEICE Trans. Inf. Syst..

Digital associative memory for word-parrallel Manhattan-distance-based vector quantization

Hans Jürgen Mattausch, Masahiro Yasuda, Seiryu Sasaki, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Measurement-Based Ring Oscillator Variation Analysis

Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika, 2010, IEEE Design & Test of Computers.

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime

Shunsuke Miyamoto, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2004, IEICE Trans. Inf. Syst..

Compact Modeling of Expansion Effects in LDMOS

Hans Jürgen Mattausch, Akihiro Tanaka, Mitiko Miura-Mattausch, 2012, IEICE Trans. Electron..

Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors

Shunsuke Miyamoto, Hans Jürgen Mattausch, Norio Sadachika, 2009, IEICE Trans. Electron..

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

Hans Jürgen Mattausch, Tetsushi Koide, Koh Johguchi, 2007, IEICE Electron. Express.

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search

Hans Jürgen Mattausch, Yuki Tanaka, Ali Ahmadi, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A Scalable Massively Parallel Processor for Real-Time Image Processing

Hans Jürgen Mattausch, Kazutami Arimoto, Takeshi Kumaki, 2011, IEEE J. Solid State Circuits.

Object tracking in video pictures based on image segmentation and pattern matching

Hans Jürgen Mattausch, Tetsushi Koide, Takashi Morimoto, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition

Fengwei An, Xiangyu Zhang, Lei Chen, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of superscalar processor with multi-bank register file

Tetsuo Hironaka, Hans Jürgen Mattausch, Tadashi Saito, 2005, 2005 IEEE International Symposium on Circuits and Systems.

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation

Kyoji Yamashita, Hans Jürgen Mattausch, Shigetaka Kumashiro, 2005, IEICE Trans. Electron..

A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry

Hans Jürgen Mattausch, Tetsushi Koide, Yuji Yano, 2003, ASP-DAC '03.

Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Power Consumption Estimation of Biped Robot During Walking

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Sandip Bhattacharya, 2019, 2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS).

High performance of short-channel MOSFETs due to an elevated central-channel doping

Hans Jürgen Mattausch, Walter Hansch, Mitiko Miura-Mattausch, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation

Mainak Sengupta, Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 2021, IEEE Access.

Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, 2021, 2021 International Symposium on Devices, Circuits and Systems (ISDCS).

Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Hideyuki Kikuchihara, 2021, 2021 International Symposium on Devices, Circuits and Systems (ISDCS).

Consistent Modeling of Snapback Phenomenon Based on Conventional I-V Measurements

Hans Jürgen Mattausch, Mitiko Miura-Mattausch, Takahiro Iizuka, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).