I. Eidner

Design study of the Bump on Flexible Lead by FEA for Wafer Level packaging

H. Reichl, O. Ehrmann, B. Wunderle, 2009, EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

Comparison of via-fabrication techniques for through-wafer electrical interconnect applications

M. Bartek, I. Eidner, J. Burghartz, 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).