Sergio D'Angelo

发表

Definition of elementary arithmetic operations by using ACM

Sergio D'Angelo, Giacomo R. Sechi, 1989, MICRO 22.

A dedicated digital unit for event recognition and centroiding in photon counting intensified CCDs

Sergio D'Angelo, Giacomo R. Sechi, Paolo Achdjian, 1995, Proceedings Seventh Euromicro Workshop on Real-Time Systems.

Heavy ion effects on configuration logic of Virtex FPGAs

A. Candelori, Sergio D'Angelo, Giacomo R. Sechi, 2005, 11th IEEE International On-Line Testing Symposium.

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs

Sergio D'Angelo, Valentino Liberali, G. Sorrenti, 2013, J. Electron. Test..

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

A fault injection tool for SRAM-based FPGAs

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

EVIDENCE: an FPGA-based system for photon event identification and centroiding

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform

Sergio D'Angelo, Giacomo R. Sechi, Sandro Pastore, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

Experimenting genetic algorithms for training a neural network prototype for photon event identification

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 1998, Proceedings of the Thirty-First Hawaii International Conference on System Sciences.

Transient and permanent fault diagnosis for FPGA-based TMR systems

Cecilia Metra, Sergio D'Angelo, Giacomo R. Sechi, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Radiation test methodology for SRAM-based FPGAs by using THESIC+

Raoul Velazco, Sergio D'Angelo, Giacomo R. Sechi, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

A fault-tolerant FPGA-based multi-stage interconnection network for space applications

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

Sergio D'Angelo, Giacomo R. Sechi, Monica Alderighi, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Novel fault-tolerant adder design for FPGA-based systems

Cecilia Metra, Sergio D'Angelo, Giacomo R. Sechi, 2001, Proceedings Seventh International On-Line Testing Workshop.

Implementing a self-checking neural system for photon event identification by SRAM-based FPGAs

Vincenzo Piuri, Sergio D'Angelo, Giacomo R. Sechi, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Modular design of communication node prototypes

Sergio D'Angelo, Giacomo R. Sechi, Stefania Russo, 1997, Proceedings Great Lakes Symposium on VLSI.

Achieving fault-tolerance by shifted and rotated operands in TMR non-diverse ALUs

Cecilia Metra, Sergio D'Angelo, Giacomo R. Sechi, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

Cecilia Metra, Sergio D'Angelo, Giacomo R. Sechi, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).