Praveen Venkataramani

Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage

Vishwani D. Agrawal, Praveen Venkataramani, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

A Test Time Theorem and its Applications

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 14th Latin American Test Workshop - LATW.

Reducing ATE Test Time by Voltage and Frequency Scaling

Praveen Venkataramani, P. Venkataramani, 2014 .

A test time theorem and its applications

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 14th Latin American Test Workshop - LATW.

ATE test time reduction using asynchronous clock period

Vishwani D. Agrawal, Praveen Venkataramani, V. Agrawal, 2013, 2013 IEEE International Test Conference (ITC).

Finding best voltage and frequency to shorten power-constrained test time

Vishwani D. Agrawal, Praveen Venkataramani, Suraj Sindia, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Sequential Quantum-Dot Cellular Automata Design And Analysis Using Dynamic

Praveen Venkataramani, 2008 .

Test-Time Reduction in ATE Using Asynchronous Clocking

Vishwani D. Agrawal, Praveen Venkataramani, 2012 .