Rakhi Narang

发表

Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges

Upasana, Rakhi Narang, Manoj Saxena, 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

Upasana, Rakhi Narang, Manoj Saxena, 2015, IEEE Transactions on Electron Devices.

Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2017, VDAT.

Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications

R. S. Gupta, Rakhi Narang, Manoj Saxena, 2012 .

Modeling and Simulation of Junctionless Double Gate Radiation Sensitive FET (RADFET) Dosimeter

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2018, IEEE Transactions on Nanotechnology.

Immunity against temperature variability and bias point invariability in double gate tunnel field effect transistor

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2012, Microelectron. Reliab..

Simulation study for Dual Material Gate Hetero-Dielectric TFET: Static performance analysis for analog applications

Upasana, Rakhi Narang, Manoj Saxena, 2013, 2013 Annual IEEE India Conference (INDICON).

Merits of designing Tunnel Field Effect Transistors with underlap near drain region

Upasana, Rakhi Narang, Manoj Saxena, 2015, 2015 Annual IEEE India Conference (INDICON).

Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2017, VDAT.

Polarity and ambipolarity controllable (PAC) tunnel field effect transistor

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Modeling and simulation of multi layer gate dielectric double gate tunnel field-effect transistor (DG-TFET)

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2011, IEEE Technology Students' Symposium.

Modeling and simulation study of short gate TFET architecture considering the impact of mobile charge carriers

Upasana, Rakhi Narang, Manoj Saxena, 2015, 2015 6th International Conference on Computers and Devices for Communication (CODEC).

Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2013 .

Drain current model for a gate all around (GAA) p-n-p-n tunnel FET

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2013, Microelectron. J..

An analytical modeling approach for a gate all around (GAA) tunnel field effect transistor (TFET)

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2012, Other Conferences.

A comparative study on the accuracy of small-signal equivalent circuit modeling for large gate periphery GaN HEMT with different source to drain length and gate width

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2021, Microelectron. J..

Analytical Model of pH sensing Characteristics of Junctionless Silicon on Insulator ISFET

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2017, IEEE Transactions on Electron Devices.

Ambipolar Behaviour of Tunnel Field Effect Transistor (TFET) as an Advantage for Biosensing Applications

Rakhi Narang, Manoj Saxena, Mridula Gupta, 2014 .