Henk Neefs

发表

On the feasibility of fixed-length block structured architectures

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 2000, Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512).

Aspects of a Fixed-Length Block Structured Instruction Set to Improve Loop Performance

Lieven Eeckhout, Henk Neefs, Jan Van Campenhout, 1998 .

An Analytical Model for Performance Estimation of Modern Data-Flow Style Scheduling Microprocessors

Henk Neefs, Jan Van Campenhout, Koen De Bosschere, 1997 .

A Microarchitecture for a fixed length Block Structured instruction set Architecture

Henk Neefs, Jan Van Campenhout, 1996 .

Early design stage exploration of fixed-length block structured architectures

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 2000, J. Syst. Archit..

Latency requirements of optical interconnects at different memory hierarchy levels of a computer system

Henk Neefs, Jan M. Van Campenhout, Pim Van Heuven, 1998, Other Conferences.

Increasing the efficiency of value prediction in future processors by predicting less

Koen De Bosschere, Henk Neefs, Bart Goeman, 1999, PARCO.

Improving Loop Performance on a Block Structured Architecture through Predication

Lieven Eeckhout, Henk Neefs, Jan Van Campenhout, 1998 .

Investigating the implementation of a block structured processor architecture in an early design stage

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture.

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 1999 .

Simulating a Modern Data-flow Scheduling Microprocessor in C++

Henk Neefs, Jan Van Campenhout, Koen De Bosschere, 1996 .

Issues in Compilation for Fixed-Length Block Structured Instruction Set Architectures

Henk Neefs, Jan Van Campenhout, Koen De Bosschere, 1997 .

A C++ Simulator modelling a modern data-flow scheduling Microprocessor

Henk Neefs, Jan Van Campenhout, Koen De Bosschere, 1996 .

An Optoelectronic 3-D Field Programmable Gate Array

Hugo Thienpont, Henk Neefs, Bart Dhoedt, 1994, FPL.

Exploitable levels of ILP in future processors

Koen De Bosschere, Henk Neefs, Jan M. Van Campenhout, 1999, J. Syst. Archit..

ESCAPE: environment for the simulation of computer architectures for the purpose of education

Henk Neefs, Jan M. Van Campenhout, Peter Verplaetse, 1998, WCAE '98.

Microarchitectural Issues of a Fixed Length Block Structured Instruction Set Architecture

Henk Neefs, Jan Van Campenhout, Koen De Bosschere, 1997 .

Optoelectronic interconnects for integrated circuits. Achievements 1996-2000.

Henk Neefs, 2000 .

Performance analysis through synthetic trace generation

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 2000, 2000 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS (Cat. No.00EX422).

A technique for high bandwidth and deterministic low latency load/store accesses to multiple cache banks

Koen De Bosschere, Henk Neefs, Hans Vandierendonck, 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

Estimating IPC of a block structured instruction set architecture in an early design stage

Lieven Eeckhout, Koen De Bosschere, Henk Neefs, 1999, PARCO.

On the Benefits of a Block Structured Instruction Set Architecture.

Lieven Eeckhout, Henk Neefs, Koen De Bosschere, 1999 .

Optical Interconnects at the L2 Cache to Main Memory Level in a Computer System and the Effect of Prefetching

Henk Neefs, Jan Van Campenhout, P Vanheuven, 1998 .

Designing a branch predictor for a block structured architecture

Henk Neefs, Frederik Habils, Koen De Bosschere, 2000 .

High-throughput genotyping of single nucleotide polymorphisms using new biplex invader technology.

Henk Neefs, Michael Olivier, Scott Law, 2002, Nucleic acids research.