Prakash Mohan Peranandam

Bounded Property Checking with Symbolic Simulation

Jürgen Ruf, Prakash Mohan Peranandam, Jürgen Ruf, 2003, MBMV.

Distributed Symbolic Bounded Property Checking

Wolfgang Rosenstiel, Roland J. Weiss, Thomas Kropf, 2006, PDMC@ICALP.

Grid Based Fast Falsification For Bounded Property Checking

Wolfgang Rosenstiel, Thomas Kropf, Jörg Behrend, 2007, FDL.

Efficient system traversal and property verification by exploiting circuit locality

Prakash Mohan Peranandam, P. Peranandam, 2006 .

Dynamic guiding of bounded property checking

Wolfgang Rosenstiel, Roland J. Weiss, Thomas Kropf, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation

Roland J. Weiss, Thomas Kropf, Jürgen Ruf, 2004, MBMV.

Using Symbolic Simulation for Bounded Property Checking

Wolfgang Rosenstiel, Thomas Kropf, Jürgen Ruf, 2003, FDL.

Fast falsification based on symbolic bounded property checking

Wolfgang Rosenstiel, Roland J. Weiss, Thomas Kropf, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Efficient System Traversal And Property Checking By Exploiting Circuit Locality

Prakash Mohan Peranandam, 2006 .

Overlap reduction in symbolic system traversal

Wolfgang Rosenstiel, Roland J. Weiss, Thomas Kropf, 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..