Abhishek Nag

An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning

Abhishek Nag, Sambhu Nath Pradhan, 2016, J. Circuits Syst. Comput..

Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique

Subhajit Das, Abhishek Nag, Sambhu Nath Pradhan, 2019, J. Circuits Syst. Comput..

Layout-oriented look up table-based dual threshold approach to reduce leakage

Abhishek Nag, Sambhu Nath Pradhan, Angshuman Chakraborty, 2015, Int. J. Comput. Aided Eng. Technol..

Design of new high-speed and low-energy dynamic PLA

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2016 .

An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA

Abhishek Nag, Sambhu Nath Pradhan, S. Pradhan, 2017 .

CG-in-PG architecture implementation for power reduction in FSMs

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2014 .

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2017, J. Circuits Syst. Comput..

Power gating architecture implementation inside clock period to reduce power

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2014, Int. J. Comput. Aided Eng. Technol..

Low power transistor level synthesis of finite state machines using a novel dual gating technique

Subhajit Das, Abhishek Nag, Sambhu Nath Pradhan, 2020 .