Sambhu Nath Pradhan

发表

An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning

Abhishek Nag, Sambhu Nath Pradhan, 2016, J. Circuits Syst. Comput..

Design of power efficient All Digital Phase Locked Loop (ADPLL)

Sambhu Nath Pradhan, Nitesh Tripathi, 2016, 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET).

Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique

Subhajit Das, Abhishek Nag, Sambhu Nath Pradhan, 2019, J. Circuits Syst. Comput..

Layout-oriented look up table-based dual threshold approach to reduce leakage

Abhishek Nag, Sambhu Nath Pradhan, Angshuman Chakraborty, 2015, Int. J. Comput. Aided Eng. Technol..

A new design of adder circuit for low power and high speed in sub-threshold region

Sambhu Nath Pradhan, Angshuman Chakraborty, 2014 .

AND-XOR Network Synthesis with Area-Power Trade-off

Santanu Chattopadhyay, Sambhu Nath Pradhan, 2008 .

Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off

Santanu Chattopadhyay, Sambhu Nath Pradhan, 2012, J. Circuits Syst. Comput..

Reduced ordered binary decision diagram-based combinational circuit synthesis for optimising area, power and temperature

Sambhu Nath Pradhan, Apangshu Das, Akash Debnath, 2019 .

A technique for power reduction of CMOS circuit at 65nm technology

Sambhu Nath Pradhan, Angshuman Chakraborty, S. Pradhan, 2012, 2012 1st International Conference on Recent Advances in Information Technology (RAIT).

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

Sambhu Nath Pradhan, Debanjali Nath, Priyanka Choudhury, 2016, J. Circuits Syst. Comput..

Power Aware Testing by Proper Don't Care Filling of Test Patterns

Sambhu Nath Pradhan, Priyanka Choudhury, Oindrila Chakraborty, 2013 .

Low power transistor level synthesis of finite state machines using a novel dual gating technique

Subhajit Das, Sambhu Nath Pradhan, Abhishek Nag, 2020, Int. J. Embed. Syst..

A New High Speed Low Power 1 Bit Full Adder

Sambhu Nath Pradhan, Angshuman Chakraborty, 2013 .

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)

Sambhu Nath Pradhan, Debanjali Nath, Priyanka Choudhury, 2013, VDAT.

FPGA and ASIC realisation of EMD algorithm for real-time signal processing

Sambhu Nath Pradhan, Debanjali Nath, Kaushik Das, 2020, IET Circuits Devices Syst..

Thermal aware output polarity selection of programmable logic arrays

Sambhu Nath Pradhan, Apangshu Das, 2015, 2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV).

Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion

Sambhu Nath Pradhan, Apangshu Das, 2018 .

Design of new high-speed and low-energy dynamic PLA

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2016 .

An efficient hardware realization of EMD for real‐time signal processing applications

Sambhu Nath Pradhan, Kaushik Das, S. Pradhan, 2020, Int. J. Circuit Theory Appl..

Facial Image Analysis for Expression Recognition by Bidimensional Empirical Mode Decomposition

Ashim Saha, Sambhu Nath Pradhan, Mameeta Pukhrambam, 2016 .

Transistor level realisation of power gated FSM

Sambhu Nath Pradhan, Debanjali Nath, Priyanka Choudhury, 2017, Int. J. Comput. Aided Eng. Technol..

Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm

Sambhu Nath Pradhan, Priyanka Choudhury, 2012, VDAT.

Design of high speed and low power full adder in sub-threshold region

Vivek Rai, Sambhu Nath Pradhan, Angshuman Chakraborty, 2016, 2016 International Conference on Microelectronics, Computing and Communications (MicroCom).

An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA

Abhishek Nag, Sambhu Nath Pradhan, S. Pradhan, 2017 .

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Sambhu Nath Pradhan, Apangshu Das, 2016, VLSI Design.

AND-XOR Network Synthesis with Area-Power Trade-off

Santanu Chattopadhyay, Sambhu Nath Pradhan, M. Tilak Kumar, 2008, 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems.

NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed-Muller Network Synthesis Using Parallel Tabular Technique

Sambhu Nath Pradhan, Apangshu Das, Yallapragada C. Hareesh, 2020, J. Circuits Syst. Comput..

Area, power and temperature optimization during binary decision diagram based circuit synthesis

Sambhu Nath Pradhan, Apangshu Das, Akash Debnath, 2017, 2017 Devices for Integrated Circuit (DevIC).

Integrated Power-Gating and State Assignment for Low Power FSM Synthesis

Santanu Chattopadhyay, Sambhu Nath Pradhan, M. Tilak Kumar, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Switching Reduction in Power Gated Design

Sambhu Nath Pradhan, Priyanka Choudhury, 2013 .

Thermal-Aware Partitioning and Encoding of Power-Gated FSM

Vivek Rai, Sambhu Nath Pradhan, Kanchan Manna, 2019, J. Circuits Syst. Comput..

Power Supply Noise Reduction of Multicore CPU by Staggering Current and Variable Clock Frequency

Sambhu Nath Pradhan, Bidyut K. Bhattacharyya, Suman Bhowmik, 2018, IEEE Transactions on Components, Packaging and Manufacturing Technology.

CG-in-PG architecture implementation for power reduction in FSMs

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2014 .

Power-area trade-off in power gated FSM synthesis

Sambhu Nath Pradhan, Priyanka Choudhury, 2016 .

Low power and high testable Finite State Machine synthesis

Sambhu Nath Pradhan, Priyanka Choudhury, 2015, 2015 International Conference and Workshop on Computing and Communication (IEMCON).

MAJORITY FUNCTION BASED ULTRA LOW POWER HIGH SPEED ADDER DESIGN USING 6 TRANSISTORS

Sambhu Nath Pradhan, Angshuman Chakraborty, 2012 .

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2017, J. Circuits Syst. Comput..

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

Sambhu Nath Pradhan, Somnath Roy Choudhury, 2020, IEEE Access.

A Technique to Reduce Leakage of CMOS Circuit at Submicron Technology

Sambhu Nath Pradhan, Angshuman Chakraborty, S. Pradhan, 2012 .

Energy Comparison of Different NOC Routers

Sambhu Nath Pradhan, Anupam Jamatia, Biman Debbarma, 2013 .

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

Sambhu Nath Pradhan, Somnath Roy Choudhury, S. Pradhan, 2019, IEEE Access.

Facial expression recognition based on eigenspaces and principle component analysis

Ashim Saha, Sambhu Nath Pradhan, 2018, Int. J. Comput. Vis. Robotics.

Thermal aware power gated design

Sambhu Nath Pradhan, Priyanka Choudhury, 2013, ARTCom 2013.

Thermal Aware SOC Testing by Introducing Cooling Period

Sambhu Nath Pradhan, Bikram Paul, Trupa Sarkar, 2017 .

Thermal aware FPRM based AND-XOR network synthesis of logic circuits

Sambhu Nath Pradhan, Apangshu Das, 2015, 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS).

Three-level AND-OR-XOR network synthesis: A GA based approach

Santanu Chattopadhyay, Sambhu Nath Pradhan, M. Tilak Kumar, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

A genetic algorithm approach for hybrid ALU design

Sambhu Nath Pradhan, Somnath Roy Choudhury, Arnab Ardhendu Purkayastha, 2015, International Conference on Computing, Communication & Automation.

Multiplexer Based Circuit Synthesis with Area-Power Trade-Off

Santanu Chattopadhyay, Sambhu Nath Pradhan, 2011 .

A Novel NOR Gate-Based Dynamic Power Gating Technique in SRAM

Sambhu Nath Pradhan, Abhishek Nag, K. Ruchira Reddy, 2020 .

Gate level leakage minimisation at 90 nm technology

Sambhu Nath Pradhan, Angshuman Chakraborty, 2013, Int. J. Comput. Aided Eng. Technol..

Thermal aware AND-OR-XOR network synthesis

Vivek Rai, Sambhu Nath Pradhan, Debanjali Nath, 2015, 2015 19th International Symposium on VLSI Design and Test.

MMaSA—A Modified Matrix Synthesis Approach for Thermal-Aware Gate Array Placement

Sambhu Nath Pradhan, Somnath Roy Choudhury, P. Sai Srinivas, 2021 .

Genetic algorithm based logic optimization and synthesis techniques with area-power trade-offs

Santanu Chattopadhyay, Sambhu Nath Pradhan, 2010 .

Power gating architecture implementation inside clock period to reduce power

Abhishek Nag, Sambhu Nath Pradhan, Debanjali Nath, 2014, Int. J. Comput. Aided Eng. Technol..

Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips

Bidyut K. Bhattacharyya, Sambhu Nath Pradhan, Suman Bhowmik, 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Leakage Reduction by Test Pattern Reordering

Sambhu Nath Pradhan, Trupa Sarkar, Shrabanti Chakraborty, 2017 .

An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis

Sambhu Nath Pradhan, Apangshu Das, S. Pradhan, 2020, Int. J. Interact. Multim. Artif. Intell..

Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback

Sambhu Nath Pradhan, Bidyut K. Bhattacharyya, Suman Bhowmik, 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together

Sambhu Nath Pradhan, Priyanka Choudhury, 2012, J. Low Power Electron..

Low power transistor level synthesis of finite state machines using a novel dual gating technique

Subhajit Das, Abhishek Nag, Sambhu Nath Pradhan, 2020 .

Low power finite state machine synthesis using power-gating

Santanu Chattopadhyay, Sambhu Nath Pradhan, M. Tilak Kumar, 2011, Integr..

Segmented Buffer for NOC Router

Sambhu Nath Pradhan, Biman Debbarma, C. Switch Allocator, 2015 .

Field-programmable gate array-based design for real-time computation of ensemble empirical mode decomposition

Sambhu Nath Pradhan, Kaushik Das, 2021, Int. J. Circuit Theory Appl..

IoT Based Design of Air Quality Monitoring System Web Server for Android Platform

Sambhu Nath Pradhan, Koel Datta Purkayastha, Ritesh Kishore Mishra, 2021, Wireless Personal Communications.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

Sambhu Nath Pradhan, Abhishek Bhattacharjee, 2021 .

Lookup table‐based negative‐bias temperature instability effect and leakage power co‐optimization using genetic algorithm approach

Sambhu Nath Pradhan, Abhishek Bhattacharjee, Dheeraj Kumar Sahu, 2021, Int. J. Circuit Theory Appl..