Che-Chia Lin

Experiments and optimizations for TVM on RISC-V Architectures with P Extension

Yi-Ru Chen, Chao-Lin Lee, Jenq-Kuen Lee, 2020, 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions

Chao-Lin Lee, Jenq-Kuen Lee, Ming-Yu Hung, 2021, ICPP Workshops.