K. Rahimunnisa

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

S. Suresh Kumar, P. Karthigaikumar, K. Rahimunnisa, 2014, Secur. Commun. Networks.

INDIAN SIGN LANGUAGE BASED STATIC HAND GESTURE RECOGNITION USING DEEP LEARNING

K. Rahimunnisa, S Gnanapriya, AKarthika, 2020 .

Low power and low area design for advanced encryption standard and fault detection scheme for secret communications

K. Rahimunnisa, T. K. Jishamol, 2013, 2013 International Conference on Communication and Signal Processing.

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

P. Karthigaikumar, K. Rahimunnisa, S. Suresh Kumar, 2013, Central European Journal of Computer Science.

ARCHITECTURAL OPTIMIZATION OF AES TRANSFORMATION SAND KEYEXPANSION

K. Rahimunnisa, S. Suresh Kumar, M. Priya Zach, 2012 .

Memory Attack Detection of Cryptographic Algorithm

K. Rahimunnisa, S. Sureshkumar, Rincy Merrin Varkey, 2011 .

Hardware Assisted Address Monitoring System

K. Rahimunnisa, Anoop Suraja A., Kavya T.S., 2010, 2010 Second International Conference on Computer Engineering and Applications.

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

P. Karthigaikumar, K. Rahimunnisa, S. Suresh Kumar, 2014 .

0.18um CMOS Technology in Implementation of S Box and a Modified S Box

K. Rahimunnisa, K. Rajeshkumar, S. Sureshkumar, 2011 .

Advanced Encryption Standard and Fault Detection for High Performance

K. Rahimunnisa, 2013 .

Efficient Techniques for the Implementation of AES SubByte and MixColumn Transformations

K. Rahimunnisa, S. Suresh Kumar, J. Jayakumar, 2012, ACITY.