Makoto Wada

A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

S. Yamada, Sumio Tanaka, Akira Umezawa, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Optimum design of dual control gate cell for high density EEPROMs

S. Inoue, M. Momodomi, Makoto Wada, 1983 .

A new flash-erase EEPROM cell with a sidewall select-gate on its source side

Shinji Taguchi, Makoto Wada, K. Naruke, 1989, International Technical Digest on Electron Devices Meeting.

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Masamitsu Oshikiri, Kiyomi Naruke, Etsushi Obi, 1991, International Electron Devices Meeting 1991 [Technical Digest].