Gregory Ruhl

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process

Paolo A. Aseron, Jason Howard, Vivek De, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 2 Tb/s 6$\,\times\,$ 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Sriram R. Vangal, Shasi Kumar, Tiju Jacob, 2011, IEEE Journal of Solid-State Circuits.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Saurabh Dighe, Sriram R. Vangal, Tiju Jacob, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

An IA-32 processor with a wide voltage operating range in 32nm CMOS

Saurabh Dighe, Shasi Kumar, Jason Howard, 2012, 2012 IEEE Hot Chips 24 Symposium (HCS).

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Saurabh Dighe, Sriram R. Vangal, Vasantha Erraguntla, 2011, IEEE Journal of Solid-State Circuits.

IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS

Saurabh Dighe, Sriram R. Vangal, Shailendra Jain, 2013, IEEE Micro.

A 2Tb/s 6×4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS

Shasi Kumar, Tiju Jacob, Vasantha Erraguntla, 2010, 2010 Symposium on VLSI Circuits.

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Saurabh Dighe, Sriram R. Vangal, Jason Howard, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

The 48-core SCC Processor: the Programmer's View

Saurabh Dighe, Sriram R. Vangal, Jason Howard, 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.