S. Mehta

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

N. Loubet, P. Kulkarni, H. Bu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell

M. Raymond, M. Burkhardt, S. Paparao, 2008, 2008 IEEE International Electron Devices Meeting.