Christian Landrault

发表

Hardware Generation of Random Single Input Change Test Sequences

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, J. Electron. Test..

Christian Landrault, 1999, J. Electron. Test..

Reducing power consumption during test application by test vector ordering

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Méthode de diagnostic unifiée pour circuits intégrés numériques

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2007 .

Guest Editorial

Christian Landrault, 2002, J. Electron. Test..

A gated clock scheme for low power scan-based BIST

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2001, Proceedings Seventh International On-Line Testing Workshop.

An alternative to fault simulation for delay-fault diagnosis

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 1992, [1992] Proceedings The European Conference on Design Automation.

An adjacency-based test pattern generator for low power BIST design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2000, Proceedings of the Ninth Asian Test Symposium.

Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solution

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2005 .

An implicit delay fault simulation method with approximate detection threshold calculation

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1993, Proceedings of IEEE International Test Conference - (ITC).

A gate resizing technique for high reduction in power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

A trace-based method for delay fault diagnosis in synchronous sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

Unified Framework for Logic Diagnosis

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 2006 .

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Power-Driven Routing-Constrained Scan Chain Design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2004, J. Electron. Test..

Hidden Markov and independence models with patterns for sequential BIST

Patrick Girard, Christian Landrault, Olivier Gascuel, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Random Adjacent Sequences

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2002 .

Is triple modular redundancy suitable for yield improvement?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009, IET Comput. Digit. Tech..

Initialization of Partially LBISTed Sequential Circuits

Christian Landrault, Marie-Lise Flottes, Isabelle Vogel, 2002 .

Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs

Arnaud Virazel, Luigi Dilillo, Christian Landrault, 2008 .

Hardware Test: Can We Learn from Software Testing?

Paolo Prinetto, Christian Landrault, Chantal Robach, 1997, VTS.

A New Reliable Method for Delay-Fault Diagnosis

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, The Fifth International Conference on VLSI Design.

Design of routing-constrained low power scan chains

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Embedded Flash Testing

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2007 .

SURF A PROGRAM FOR DEPENDABILITY EVALUATlON OF COMPLEX FAULT-TOLERANT COMPUTING SYSTEMS

Christian Landrault, Jean-Claude Laprie, Alain Costes, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

SoC Yield Improvement: Redundant Architectures to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Test Conference.

Power-Aware Scan Testing for Peak Power Reduction

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2005 .

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2001, J. Electron. Test..

Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults

Christian Landrault, Jean-Claude Laprie, Alain Costes, 1978, IEEE Transactions on Computers.

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

João Paulo Teixeira, Serge Pravossoudovitch, Christian Landrault, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Guest Editorial

Christian Landrault, 2003, J. Electron. Test..

Test power: a big issue in large SOC designs

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

A Mixed Approach for Unified Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Power driven chaining of flip-flops in scan architectures

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2002, Proceedings. International Test Conference.

Delay fault diagnosis in sequential circuits based on path tracing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Integr..

DFSIM: a gate-delay fault simulator for sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings ED&TC European Design and Test Conference.

Is TMR Suitable for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2009 .

A diagnostic ATPG for delay faults based on genetic algorithms

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Is high level test synthesis just design for test?

Christian Landrault, Bruno Rouzeyre, Marie-Lise Flottes, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

Low power BIST by filtering non-detecting vectors

Christian Landrault, Salvador Manich, Joan Figueras, 1999, ETW.

A Gated Clock Scheme for Low Power Testing of Logic Cores

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, J. Electron. Test..

SoC Yield Improvement for Future Nanoscale Technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, ETS 2009.

A New Scan-BIST Structures to Test delay Faults in Sequential Circuits

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 1998 .

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors

Christian Landrault, Lew Fock Chong Lew Yan Voon, Christian Dufaza, 1992, The Fifth International Conference on VLSI Design.

A novel approach to delay-fault diagnosis

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

On using machine learning for logic BIST

Patrick Girard, Christian Landrault, Christophe Fagot, 1997, Proceedings International Test Conference 1997.

Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan Testing

Serge Pravossoudovitch, Christian Landrault, Nabil Badereddine, 2006 .

Yield Improvement, Fault-Tolerance to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Delay-fault diagnosis by critical-path tracing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1992, IEEE Design & Test of Computers.

Low power BIST design by hypergraph partitioning: methodology and architectures

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor

Yves Crouzet, Christian Landrault, C. Landrault, 1980, IEEE Transactions on Computers.

Framework for Logic Diagnosis

Arnaud Virazel, Christian Landrault, Patrick Girard, 2006 .

Interconnect Capacitance Modelling in a VDSM CMOS Technology

Christian Landrault, Pascal Nouet, David Bernard, 2001, VLSI-SOC.

Circuit partitioning for low power BIST design with minimized peak power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Switch level test pattern production for CMOS ICs

Serge Pravossoudovitch, Christian Landrault, Marie-Lise Flottes, 1991, [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications.

An overview of failure mechanisms in embedded flash memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 24th IEEE VLSI Test Symposium.

Guest Editorial

Christian Landrault, 2000, J. Electron. Test..

High Defect Coverage with Low-Power Test Sequences in a BIST Environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, IEEE Des. Test Comput..

On using efficient test sequences for BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

A test vector inhibiting technique for low energy BIST design

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Functional Memory Testing

Christian Landrault, 2004 .

On hardware generation of random single input change test sequences

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2001, IEEE European Test Workshop, 2001..

Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année)

Christian Landrault, Florence Azaïs, Michel Renovell, 2002 .

An optimized BIST test pattern generator for delay testing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

A Unified DFT Approach for BIST and External Test

Christian Landrault, Marie-Lise Flottes, A. Petitqueux, 2003, J. Electron. Test..

A ring architecture strategy for BIST test pattern generation

Patrick Girard, Christian Landrault, Olivier Gascuel, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Testability improvements using e-beam controllability: principle and design for electron-beam testability

Christian Landrault, Pascal Nouet, 1996 .

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

Christian Landrault, Marie-Lise Flottes, A. Petitqueux, 2000, Proceedings of the Ninth Asian Test Symposium.

Improving Diagnosis Resolution without Physical Information

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, J. Electron. Test..

Reliable method for delay-fault diagnosis

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 1991 .

Something I Always Wanted to Know About Test, But Was Afraid to Ask

Christian Landrault, 2009, ETS.

DERRIC: A Tool for Unified Logic Diagnosis

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2007, 12th IEEE European Test Symposium (ETS'07).

Automatic testability analysis of boards and MCMs at chip level

Christian Landrault, Marc Perbost, Ludovic Le Lan, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

A Ring Architecture Strategy for BIST Test Pattern Generation

Patrick Girard, Christian Landrault, Olivier Gascuel, 2003, J. Electron. Test..

RSIC Generation: A Solution for Logic BIST

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2008 .

Random Adjacent Sequences: An Efficient Solution for Logic BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2001, VLSI-SOC.

Table of Contents: ATS 2006 Proceedings of the 15 th Asian Test Symposium

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2006 .

Parametric Analysis of 2-Unit Redundant Computer Systems With Corrective and Preventive Maintenance

Christian Landrault, Jean-Claude Laprie, Alain Costes, 1981, IEEE Transactions on Reliability.

Test de Circuits et de Systèmes Intégrés

Christian Landrault, Florence Azaïs, Michel Renovell, 2004 .

Low Power BIST by Filtering Non-Detecting Vectors

João Paulo Teixeira, Patrick Girard, Serge Pravossoudovitch, 1999, European Test Workshop 1999 (Cat. No.PR00390).

An advanced diagnostic method for delay faults in combinational faulty circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, J. Electron. Test..

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

Power Conscious Testing

Christian Landrault, Patrick Girard, Y. Bonhomme, 2003 .

A non-iterative gate resizing algorithm for high reduction in power consumption

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Integr..

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2009, J. Electron. Test..

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 1999, J. Electron. Test..

Efficient scan chain design for power minimization during scan testing under routing constraint

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Génération automatique de vecteurs de test au niveau transistor

Christian Landrault, Serge Pravossoudovitch, Marie-Lise Flottes, 1989 .

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems

Christian Landrault, Jean-Claude Laprie, 1978, Jerusalem Conference on Information Technology.

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

A new test pattern generation method for delay fault testing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1996, Proceedings of 14th VLSI Test Symposium.

Diagnostic of path and gate delay faults in non-scan sequential circuits

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Editorial

Erik Jan Marinissen, Christian Landrault, 2007, IET Comput. Digit. Tech..

Unified Diagnostic Method Targeting Several Fault Models

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2006 .

A modified clock scheme for a low power BIST test pattern generator

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

BIST linear generator based on complemented outputs

Christian Landrault, Lew Fock Chong Lew Yan Voon, Christian Dufaza, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

Fault modeling and fault equivalence in CMOS technology

Serge Pravossoudovitch, Christian Landrault, Marie-Lise Flottes, 1990, EURO-DAC '90.

Goovtant: an efficient mixed level ATPG to test realistic faults in complex CMOS circuits

Serge Pravossoudovitch, Christian Landrault, Marie-Lise Flottes, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Technique de reset partiel pour BIST de circuits séquentiels

Christian Landrault, M.-L. Flottes, A. Petitqueux, 1999 .

A BIST structure to test delay faults in a scan environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

Christian Landrault, Pascal Nouet, David Bernard, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

A test vector ordering technique for switching activity reduction during test operation

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Using TMR Architectures for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Reliability andAvailability Models for

Christian Landrault, Jean-Claude Laprie, Alain Costes, 1978 .

Parametric Analysis of2-Unit Redundant Computer Systems WithCorrective andPreventive Maintenance

Christian Landrault, Jean-Claude Laprie, Alain Costes, 1981 .

Delay-fault diagnosis based on critical path tracing from symbolic simulation

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.