Kazuhiko Iijima

Arbitrarily-Sized Module Location Technique in the LOP System

Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu, 1982, DAC 1982.

Partitioning and Placement Technique for Bus-Structured PWB

Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu, 1983, 20th Design Automation Conference Proceedings.

Knowledge-Based Placement Technique for Printed Wiring Boards

Kazutoshi Wakabayashi, Gotaro Odawara, Kazuhiko Iijima, 1985, DAC 1985.

Timing-oriented routers for PCB layout design of high-performance computers

Terumine Hayashi, Masahiro Takakura, Mitsuho Seki, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Some Placement Techniques for PWB's

Gotaro Odawara, Kazuhiko Iijima, 1987 .

Reduction of Delay/Area Overhead on Test Point Insertion for Scan-Based BIST

Kazumi Hatayama, Michinobu Nakao, Seiji Kobayashi, 1998 .

Knowledge-Based Placement Technique for Printed Wiring Boards

Kazutoshi Wakabayashi, Gotaro Odawara, Kazuhiko Iijima, 1985, 22nd ACM/IEEE Design Automation Conference.

Arbitrarily-Sized Module Location Technique in the LOP System

Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu, 1982, 19th Design Automation Conference.

PAS-LOP: An Automatic Module Location System for PWB

Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu, 1981, 18th Design Automation Conference.

Low overhead test point insertion for scan-based BIST

Kazumi Hatayama, Michinobu Nakao, Seiji Kobayashi, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A Rule-Based Placement System for Printed Wiring Boards

Gotaro Odawara, Kazuhiko Iijima, Y. Dai, 1987, 24th ACM/IEEE Design Automation Conference.