Hidenobu Miyamoto

A 0.18-μm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO (Special Issue on Low-Power and High-Speed LSI Technologies)

Masayuki Mizuno, Koichiro Furuta, Takeshi Andoh, 1997 .

and Repair Function

Hiroki Koike, Masahide Takada, Hidenobu Miyamoto, 1990 .

A 0.18 /spl mu/m CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator

Masayuki Mizuno, Takeshi Andoh, T. Tamura, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

0.15μm CMOS Devices with Reduced Junction Capacitance

Masao Fukuma, Akira Tanabe, Hidenobu Miyamoto, 1995 .

Self-Test and

Hiroki Koike, Toshio Takeshima, Masahide Takada, 1992 .

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Hiroki Koike, Takaho Tanigawa, Hidenobu Miyamoto, 1992 .

Stopper-less hybrid low-k/Cu DD structure fabrication combined with low-k CMP

Hidenobu Miyamoto, Tatsuya Usami, M. Tagami, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

0.15 /spl mu/m CMOS with high reliability and performance

Masao Fukuma, Akira Tanabe, Hidenobu Miyamoto, 1993, Proceedings of IEEE International Electron Devices Meeting.

A 0 . 1m Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy

Chenming Hu, Hidenobu Miyamoto, Toru Tatsumi, 1998 .

Suppression of bimodal stress-induced voiding using high-diffusive dopant from Cu-alloy seed layer

Hidenobu Miyamoto, K. Motoyama, K. Fujii, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).