Kunihiro Komiyaji

A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

Yoji Nishio, Yoshitaka Kinoshita, Atsushi Hiraishi, 1997 .

FA 13.2: A 7ns 140mW 1Mb CMOS SRAM with Current Sense Amplifier

Fumio Kojima, Toshiaki Yamanaka, Akihiro Shimizu, 1990 .

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Toshiaki Yamanaka, Katsuro Sasaki, Sadayuki Morita, 1994 .

A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

Toshiaki Yamanaka, Masataka Minami, Koichiro Ishibashi, 1995 .

Hot-Carrier Effects under Pulsed Stress in CMOS Devices

Kazuo Yano, Toshiaki Masuhara, Kunihiro Komiyaji, 1987, 1987 Symposium on VLSI Technology. Digest of Technical Papers.

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

Koichiro Ishibashi, H. Toyoshima, Toshiaki Yamanaka, 1992 .

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

Koichiro Ishibashi, H. Toyoshima, Takashi Nishida, 1994 .