J. Y. Wu

发表

Simulation and evaluation of a CCHP system with exhaust gas deep-recovery and thermoelectric generator

C. Y. Zheng, Wang Jialong, J. Y. Wu, 2014 .

CMP process development for the via-middle 3D TSV applications at 28nm technology node

J. Y. Wu, Jen-Chieh Lin, T. Tsai, 2012 .

Process development of high-k metal gate aluminum CMP at 28nm technology node

J. Y. Wu, T. Tsai, Welch Lin, 2012 .

Process development of replacement metal gate Tungsten chemical mechanical polishing on 14nm technology node and beyond

J. Y. Wu, C. C. Liu, J. F. Lin, 2015, 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).

Characteristics of HfZrOx gate stack engineering for reliability improvement on 28nm HK/MG CMOS technology

S. F. Tzou, C. G. Chen, J. Y. Wu, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application

Shunpei Yamazaki, Shao Hui Wu, Chi Chang Shuai, 2016, 2016 IEEE Symposium on VLSI Technology.

Defect reduction with CMP pad dressing optimization

Wu-Sian Sie, J. Y. Wu, Chun-Lin Chen, 2014, Proceedings of International Conference on Planarization/CMP Technology 2014.

Investigation of the structural and electrical characterization on ZrO2 addition for ALD HfO2 with La2O3 capping layer integrated metal-oxide semiconductor capacitors

J. Y. Wu, C. C. Liu, S. J. Wang, 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

The Amorphous-Si CMP process improvement for L14 nm FinFET technology node

J. Y. Wu, C. C. Liu, Y. M. Lin, 2014, Proceedings of International Conference on Planarization/CMP Technology 2014.

A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric

J. Y. Wu, C. C. Liu, S. J. Wang, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Investigation of aluminum film properties and microstructure for replacement metal gate application

J. Y. Wu, M. Tsai, T. Tsai, 2013 .

Evaluation of aluminum film properties and microstructure for replacement metal gate application at 28nm technology node

J. Y. Wu, C. Hsu, M. Tsai, 2011, 2011 IEEE International Interconnect Technology Conference.

Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

J. Y. Wu, C. C. Liu, Wen-Chin Lin, 2012 .

Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

J. Y. Wu, Y. M. Lin, C. H. Chen, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Development of a Production Worthy Non-Selective Slurry W-CMP for Logic Applications at 28nm Technology Node and Beyond

Yan Chen, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, 2010 .

Optimized copper chemical mechanical polishing with CVD Co barrier at 14nm technology node

J. Y. Wu, Y. M. Lin, Y. L. Liu, 2014, Proceedings of International Conference on Planarization/CMP Technology 2014.

Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)

J. Y. Wu, M. Chudzik, B. Colombeau, 2016, 2016 IEEE Symposium on VLSI Technology.

A novel hydrogen rich interfacial layer to downscale high-K dielectrics

J. Y. Wu, M. Chan, S. Wang, 2010, International Conference on Advanced Thermal Processing of Semiconductors.

Effects of La2O3 Capping Layers Prepared by Different ALD Lanthanum Precursors on Flatband Voltage Tuning and EOT Scaling in TiN/HfO2/SiO2/Si MOS Structures

J. Y. Wu, C. C. Liu, Shui-Jinn Wang, 2011 .

p-Type MOSFET Contact Resistance Improvement by Conformal Plasma Doping and Nanosecond Laser Annealing

C. I. Li, J. Y. Wu, M. Chudzik, 2019, IEEE Electron Device Letters.

Alleviating eSiGe Strain Relaxation Using Cryo-Implantation

C. I. Li, J. Y. Wu, B. Colombeau, 2011 .

Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology

T. Y. Lu, C. I. Li, Y. S. Huang, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation

C. I. Li, J. Y. Wu, I. Chen, 2011, 11th International Workshop on Junction Technology (IWJT).

The TDDB failure mode and its engineering study for 45nm and beyond in porous low k dielectrics direct polish scheme

J. Y. Wu, Wen-Chin Lin, D. Perng, 2010, IEEE International Reliability Physics Symposium.

A comprehensive process engineering on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40nm technology node and beyond

Jack Lin, J. Y. Wu, C. C. Liu, 2011, 2011 International Reliability Physics Symposium.

Defect study of manufacturing feasible porous low k dielectrics direct polish for 45nm technology and beyond

Dung-Ching Perng, J. Y. Wu, A. Yu, 2009, 2009 IEEE International Interconnect Technology Conference.