Hasitha Muthumala Waidyasooriya

发表

FPGA-Oriented Parallel Programming

Masanori Hariyama, Kunio Uchiyama, Hasitha Muthumala Waidyasooriya, 2018 .

Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors

Hasitha Muthumala Waidyasooriya, Hariyama Masanori, Kameyama Michitaka, 2011 .

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2008, IEICE Trans. Electron..

Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2010, ERSA.

FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Evaluation of a Heterogeneous Multi-Core Architecture for Multimedia Applications

Hasitha Muthumala Waidyasooriya, Hariyama Masanori, Kameyama Michitaka, 2009 .

Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL

Masanori Hariyama, Kota Kasahara, Hasitha Muthumala Waidyasooriya, 2016, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS).

OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology

Masanori Hariyama, Shunsuke Tatsumi, Hasitha Muthumala Waidyasooriya, 2017, IEEE Transactions on Parallel and Distributed Systems.

Exploiting the Memory Hierarchy

Masanori Hariyama, Kunio Uchiyama, Hasitha Muthumala Waidyasooriya, 2018 .

FPGA-Based Acceleration of Word2vec using OpenCL

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yuichiro Aoki, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2-D FDTD Computation

Hasitha Muthumala Waidyasooriya, Hariyama Masanori, Kameyama Michitaka, 2012 .

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2012, IEICE Trans. Inf. Syst..

Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, 2019 .

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Platform and Mapping Methodology for Heterogeneous Multicore Processors

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2012 .

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Tsukasa Endo, 2017, Int. J. Reconfigurable Comput..

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, H. M. Waidyasooriya, 2019, IEEE Access.

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

Masanori Hariyama, Michitaka Kameyama, Kunio Uchiyama, 2012, IEICE Trans. Electron..

Hybrid Single/Double Precision Floating-Point Computation on GPU Accelerators for 2-D FDTD

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2013 .

A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yuichiro Aoki, 2019, 2019 Seventh International Symposium on Computing and Networking Workshops (CANDARW).

Introduction to OpenCL for FPGA

Masanori Hariyama, Kunio Uchiyama, Hasitha Muthumala Waidyasooriya, 2018 .

Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Chia-Yin Liu, 2019, 2019 Seventh International Symposium on Computing and Networking (CANDAR).

OpenCL-based design of an FPGA accelerator for quantum annealing simulation

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Masayuki Ohzeki, 2019, The Journal of Supercomputing.

FPGA-accelerated Searchable Encrypted Database Management Systems for Cloud Services

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Mitsuhiro Okada, 2020 .

FPGA Accelerator Design Using OpenCL

Masanori Hariyama, Kunio Uchiyama, Hasitha Muthumala Waidyasooriya, 2018 .

Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems

Masaaki Harada, Masanori Hariyama, Hasitha Muthumala Waidyasooriya, 2018, SCFA.

Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2010, ERSA.

FPGAAccelerator for DNA Sequence Alignment Based on an Ef ficient DataDependent Memory Access Scheme

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2014 .

FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, 2016, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS).

Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2014, J. Comput. Eng..

Benchmarks for FPGA-Targeted High-Level-Synthesis

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, 2019, 2019 Seventh International Symposium on Computing and Networking (CANDAR).

Architecture of an FPGA accelerator for LDA-based inference

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Tsukasa Ishigaki, 2017, 2017 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD).

Automatic Optimization of OpenCL-Based Stencil Codes for FPGAs

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Tsukasa Endo, 2017 .

A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, H. M. Waidyasooriya, 2020, IEEE Access.

Hardware-oriented succinct-data-structure based on block-size-constrained compression

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Daisuke Ono, 2015, 2015 7th International Conference of Soft Computing and Pattern Recognition (SoCPaR).

Design of FPGA-Based Computing Systems with OpenCL

Masanori Hariyama, Kunio Uchiyama, Hasitha Muthumala Waidyasooriya, 2017 .

Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, H. M. Waidyasooriya, 2016, IEEE Transactions on Parallel and Distributed Systems.

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2009, IEICE Trans. Electron..

Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2008, ERSA.

Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2013, 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Yusuke Araki, 2018, 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2011, IEEE Transactions on Circuits and Systems for Video Technology.

OpenCL-Based Implementation of an FPGA Accelerator for Molecular Dynamics Simulation

Masanori Hariyama, Kota Kasahara, Hasitha Muthumala Waidyasooriya, 2017 .

Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL

Masanori Hariyama, Kota Kasahara, Hasitha Muthumala Waidyasooriya, 2016, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS).

Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2009, ERSA.

Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators

Masanori Hariyama, Hasitha Muthumala Waidyasooriya, H. M. Waidyasooriya, 2021, J. Supercomput..

An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure

Masanori Hariyama, Michitaka Kameyama, Hasitha Muthumala Waidyasooriya, 2015 .

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Hasitha Muthumala Waidyasooriya, H. M. Waidyasooriya, M. Hariyama, 2022, IEEE Access.