Elizabeth J. Brauer

发表

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells

Elizabeth J. Brauer, Stéphane Badel, Yusuf Leblebici, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Functional verification of ECL circuits including voltage regulators

Elizabeth J. Brauer, Sung-Mo Kang, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP

Elizabeth J. Brauer, Yusuf Leblebici, Armin Tajalli, 2009, Microelectron. J..

An analytic method to calculate emitter follower delay using trial functions in coupled node equations

Elizabeth J. Brauer, Sung-Mo Kang, E. J. Brauer, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic

Elizabeth J. Brauer, Yusuf Leblebici, 2004, Circuits, Signals, and Systems.

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design

Elizabeth J. Brauer, Stéphane Badel, Yusuf Leblebici, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A full-swing bootstrapped BiCMOS buffer

Elizabeth J. Brauer, Pradeep Elamanchili, 1997, Proceedings Great Lakes Symposium on VLSI.

Improving the power-delay product in SCL circuits using source follower output stage

Elizabeth J. Brauer, Massimo Alioto, Yusuf Leblebici, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Additive Decomposition Applied to the Semiconductor Drift-Diffusion Model

Elizabeth J. Brauer, James M. McDonough, Marek Turowski, 1998, VLSI Design.

Hardware implementation of a neural network pattern shaper algorithm

Elizabeth J. Brauer, James J. Abbas, Joshua Colvin, 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

Low noise MCML prefix adders using 0.18 µm CMOS technology

Elizabeth J. Brauer, Yusuf Leblebici, 2004, Circuits, Signals, and Systems.

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Elizabeth J. Brauer, Massimo Alioto, Yusuf Leblebici, 2008, PATMOS.

Analog circuit model of lamprey unit pattern generator

Elizabeth J. Brauer, James J. Abbas, Ranu Jung, 1997, Proceedings Great Lakes Symposium on VLSI.

An algorithm for functional verification of digital ECL circuits

Elizabeth J. Brauer, Sung-Mo Kang, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Finding efficient inductor geometries in digital CMOS process for RF applications

Elizabeth J. Brauer, Vikram Magoon, 2004, Circuits, Signals, and Systems.