Tad A. Kwasniewski

发表

Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel

Jinguang Jiang, Bo Wang, Dianyong Chen, 2009, 2009 11th International Conference on Computer Modelling and Simulation.

Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

Tad A. Kwasniewski, Tingjun Wen, 2008, 2008 IEEE International Behavioral Modeling and Simulation Workshop.

Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications

Miao Li, Tad A. Kwasniewski, Peter Noel, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

A DLL fractional M/N frequency synthesizer

Tad A. Kwasniewski, Haizheng Guo, 2015, 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE).

A 0.18μm CMOS Receiver with Decision-feedback Equalization for Backplane Applications

Miao Li, Tad A. Kwasniewski, Shoujun Wang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A DLL-based fractional-N frequency synthesizer with a programmable injection clock

Tad A. Kwasniewski, Haizheng Guo, 2012, 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

Jinguang Jiang, Bo Wang, Dianyong Chen, 2009, 2009 Canadian Conference on Electrical and Computer Engineering.

A 0.18/spl mu/m CMOS clock and data recovery circuit with extended operation range

Wenjie Huang, Miao Li, Tad A. Kwasniewski, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A multi-mode sphere detector architecture for WLAN applications

Tad A. Kwasniewski, Ramin Shariat-Yazdi, 2008, 2008 IEEE International SOC Conference.

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2006, 2006 Canadian Conference on Electrical and Computer Engineering.

A signal integrity-based link performance simulation platform

Tad A. Kwasniewski, Rakesh H. Patel, William Bereza, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Real‐time cepstral analysis, speech feature extraction, for the cochlear prosthesis

Tad A. Kwasniewski, Ibrahim J. Gedeon, Timothy J. Rahrer, 1989 .

Spur analysis and reduction of edge combining DLL-based frequency multiplier

Xinjie Wang, Tad A. Kwasniewski, Haizheng Guo, 2013, 2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

A monolithic high modulation efficiency CMOS laser diode / modulator driver

Bo Wang, Zhigong Wang, Dianyong Chen, 2009, 2009 International Conference on Telecommunications.

A 42-Gb/s Decision Circuit in 0.13µm CMOS

Dianyong Chen, Bangli Liang, Tad A. Kwasniewski, 2008, 6th Annual Communication Networks and Services Research Conference (cnsr 2008).

A 0.18-μm CMOS clock and data recovery circuit with reference-less dual loops

Miao Li, Tad A. Kwasniewski, Shoujun Wang, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology

Miao Li, Tad A. Kwasniewski, Shoujun Wang, 2005, ASP-DAC.

A 0.18 /spl mu/m CMOS transceiver design for high-speed backplane data communications

Wenjie Huang, Miao Li, Tad A. Kwasniewski, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example

Zhe Jiang, Tad A. Kwasniewski, Haizheng Guo, 2015, 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE).

PELE: Pre-emphasis & Equalization Link Estimator to Address the Effects of Signal Integrity Limitations

Tad A. Kwasniewski, Rakesh H. Patel, William Bereza, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

PLL-based fractional-N frequency synthesizers

Tad A. Kwasniewski, Peter Noel, Farhad Zarkeshvari, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

Bang-Bang CDR's acquisition, locking, and jitter tolerance

Chao He, Tad A. Kwasniewski, 2012, 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane

Tad A. Kwasniewski, Charles E. Berndt, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

Behavioral test benches for digital clock and data recovery circuits using Verilog-A

Tad A. Kwasniewski, S. I. Ahmed, Kent Orthner, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Decision feedback equalization for high-speed backplane data communications

Jing Chen, Miao Li, Tad A. Kwasniewski, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology

Muhammad Usama, Tad A. Kwasniewski, 2007, 2007 IEEE International Symposium on Circuits and Systems.

An eye detection technique for clock and data recovery applications

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis

Tad A. Kwasniewski, Thierry Lepley, Lizhong Sun, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously

Bo Wang, Dianyong Chen, Bangli Liang, 2009, 2009 Canadian Conference on Electrical and Computer Engineering.

A full-rate truly monolithic CMOS CDR for low-cost applications

Bo Wang, Zhigong Wang, Dianyong Chen, 2009, 2009 Canadian Conference on Electrical and Computer Engineering.

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2006, 2006 IEEE International SOC Conference.

Is High Frequency Analog DFT Possible?

Bozena Kaminska, Linda S. Milor, Jérôme Wojcik, 1996, VTS.

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission

Lei Zhang, Tad A. Kwasniewski, 2009, Microelectron. J..

2.4 GHz RF down-conversion mixers in standard CMOS technology

Tad A. Kwasniewski, Arif A. Siddiqi, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A novel fractional-N PLL architecture with hybrid of DCO and VCO

Chao He, Tad A. Kwasniewski, 2012, 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system

Tad A. Kwasniewski, Peter Noel, Harry Tai, 2011, 2011 IEEE International SOC Conference.

Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops

David D. Falconer, Tad A. Kwasniewski, P. Mohanraj, 1991, IEEE J. Sel. Areas Commun..

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

Huong Ho, Tad A. Kwasniewski, Valek Szwarc, 2009, Int. J. Reconfigurable Comput..

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Optimized LNA for analog RF front-end circuit in brain-machine interface

Bo Wang, Robert Sobot, Bangli Liang, 2010, 2010 IEEE International Conference on Wireless Communications, Networking and Information Security.

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2005, Circuits, Signals, and Systems.

Turbo codes - digital IC design

Tad A. Kwasniewski, Moeed Israr, 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).

Design and comparison of CMOS Current Mode Logic latches

Muhammad Usama, Tad A. Kwasniewski, T. Kwasniewski, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A chip set for pipeline and parallel pipeline FFT architectures

Tad A. Kwasniewski, Valek Szwarc, Wilson Wong, 1994, J. VLSI Signal Process..

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops

Tad A. Kwasniewski, Rakesh H. Patel, William Bereza, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Design Considerations for a Direct RF Sampling Mixer

Wei Wang, Dianyong Chen, Tad A. Kwasniewski, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops

Krzysztof Iniewski, Tad A. Kwasniewski, Lizhong Sun, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation

Tad A. Kwasniewski, Ramin Shariat-Yazdi, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A DLL-based period synthesis

Tad A. Kwasniewski, Haizheng Guo, 2015, 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE).

A reduced reference spur multiplying delay-locked loop

Xinjie Wang, Tad A. Kwasniewski, 2016, Int. J. Circuit Theory Appl..

An all-digital data recovery circuit optimization using Matlab/Simulink

Tad A. Kwasniewski, S. I. Ahmed, 2005, 2005 IEEE International Symposium on Circuits and Systems.

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2006, IEEE Custom Integrated Circuits Conference 2006.

A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems

Samy A. Mahmoud, Tad A. Kwasniewski, Wilf P. LeBlanc, 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

Huong Ho, Tad A. Kwasniewski, Valek Szwarc, 2010, J. Signal Process. Syst..

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application

Tad A. Kwasniewski, Jingcheng Zhuang, Qingjin Du, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Simulator for High-Speed Backplane Transceivers

Bo Wang, Dianyong Chen, Bangli Liang, 2009, 2009 11th International Conference on Computer Modelling and Simulation.