George Economakos

发表

Bit level architectural exploration technique for the design of low power multipliers

George Economakos, Kostas Anagnostopoulos, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Efficient High-Level Coding in a PLC to FPGA Translation and Implementation Flow

George Economakos, Christoforos Economakos, C. Economakos, 2015 .

A reconfigurable IP characterization technique improving high-level synthesis results

Dimitrios Soudris, Efstathios Sotiriou-Xanthopoulos, George Economakos, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Behavioral synthesis with SystemC and PSL assertions for interface specification

George Economakos, G. Economakos, 2006, 2006 IEEE International Symposium on Circuits and Systems.

HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

Automated FPGA implementation methodology of PLC programs with floating point operations

George Economakos, Christoforos Economakos, Ioannis Koutras, 2010, 2010 IEEE International Symposium on Industrial Electronics.

Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A predecoding technique for ILP exploitation in Java processors

Kiamal Z. Pekmestzi, George Economakos, Isidoros Sideris, 2008, J. Syst. Archit..

Co-design of many-accelerator heterogeneous systems exploiting virtual platforms

Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

High-level synthesis with reconfigurable datapath components

George Economakos, G. Economakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Automated synthesis of an FPGA-based controller for vehicle lateral control

George Economakos, Christoforos Economakos, Michael G. Skarpetis, 2016 .

Language based design verification with semantic analysis

George K. Papakonstantinou, George Economakos, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Exploiting the use of VHDL specifications in the AGENDA high-level synthesis environment

George K. Papakonstantinou, George Economakos, G. Papakonstantinou, 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

Performance analysis and complexity study of LDPC and turbo coding schemes for inter vehicle communications

Angelos Amditis, Nikolaos K. Uzunoglu, George Economakos, 2011, 2011 11th International Conference on ITS Telecommunications.

Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

A standard-cell library suite for deep-deep sub-micron CMOS technologies

Dimitrios Soudris, Antonis Papanikolaou, George Economakos, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

High Performance and Area Efficient Flexible DSP Datapath Synthesis

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Program-based and model-based PLC design environment for multicore FPGA architectures

George Economakos, Christoforos E. Economakos, Michael G. Skarpetis, 2014, 2014 11th International Conference on Informatics in Control, Automation and Robotics (ICINCO).

A virtual platform for exploring hierarchical interconnection for many-accelerator systems

Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

Behavioral synthesis of digital filters using attribute grammars

George K. Papakonstantinou, Panayiotis Tsanakas, George Economakos, 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

A scalable FPGA-based architecture for digital controllers and a corresponding rapid prototyping design methodology

Maria P. Tzamtzi, George Economakos, Christoforos E. Economakos, 2014, 2014 IEEE 23rd International Symposium on Industrial Electronics (ISIE).

Animation techniques for real time ECG monitoring

George K. Papakonstantinou, George Economakos, L. Nikolaidis, 1998, Computers in Cardiology 1998. Vol. 25 (Cat. No.98CH36292).

An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures

Jürgen Becker, Dimitrios Soudris, Kostas Siozios, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2014 .

High-level synthesis heuristics for run-time reconfigurable architectures

Sotirios Xydis, George Economakos, 2007, 2007 15th European Signal Processing Conference.

A framework for rapid evaluation of heterogeneous 3-D NoC architectures

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2014, Microprocess. Microsystems.

A Methodology for Design Space Exploration in Embedded DSP Applications

George Economakos, Kostas Anagnostopoulos, Isidoros Sideris, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

A complete specification and implementation methodology for high-level hardware transformations

George K. Papakonstantinou, George Economakos, Ioannis Drositis, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

Efficient serial and parallel implementation of programmable fir filters based on the merging technique

Kiamal Z. Pekmestzi, George Economakos, Dimitris Bekiaris, 2008, 2008 16th European Signal Processing Conference.

Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2014, TECS.

Handling advanced scheduling heuristics under a hardware compiler generation environment

George K. Papakonstantinou, George Economakos, Petros Oikonomakos, 2002, Knowl. Based Syst..

A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2007, 2007 15th European Signal Processing Conference.

Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments

Dimitrios Soudris, Efstathios Sotiriou-Xanthopoulos, George Economakos, 2012, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2009, Integr..

A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2008, 2008 16th European Signal Processing Conference.

Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

An Attribute Grammar Driven High-Level Synthesis Paradigm for Control Applications

George K. Papakonstantinou, George Economakos, G. Papakonstantinou, 1999 .

ESL as a Gateway from OpenCL to FPGAs: Basic Ideas and Methodology Evaluation

George Economakos, G. Economakos, 2012, 2012 16th Panhellenic Conference on Informatics.

BIT-width exploration over 3D architectures using high-level synthesis

Dimitrios Soudris, Antonis Papanikolaou, George Economakos, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis

George Economakos, Christoforos E. Economakos, 2008, 2008 IEEE International Conference on Emerging Technologies and Factory Automation.

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework

Kiamal Z. Pekmestzi, Dimitrios Soudris, Antonis Papanikolaou, 2010, PATMOS.

Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging

Dimitrios Soudris, Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, 2014, 2014 4th International Conference on Wireless Mobile Communication and Healthcare - Transforming Healthcare Through Innovations in Mobile and Wireless Technologies (MOBIHEALTH).

A top-down interactive behavioral synthesis environment

George K. Papakonstantinou, George Economakos, I. P. Poulakis, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

Interaction in language based system level design using an advanced compiler generator environment

George Economakos, Panayotis Tsanakas, I. P. Poulakis, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures

Alexandros Bartzas, George Economakos, A. Bartzas, 2012, Euro-Par Workshops.

A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2010, ISVLSI.

A mixed style multiplier architecture for low dynamic and leakage power dissipation

George Economakos, Kiamal Pekmestzi, Dimitris Bekiaris, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models

Jürgen Becker, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs?

Dimitrios Soudris, Dionysios Diamantopoulos, George Economakos, 2013, IEEE International Symposium on Signal Processing and Information Technology.

Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain

George Economakos, Dimitris Bekiaris, 2012, 2012 15th Euromicro Conference on Digital System Design.

Behavioral synthesis with SystemC

George K. Papakonstantinou, George Economakos, Petros Oikonomakos, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2016, ACM Trans. Embed. Comput. Syst..

Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis

George Economakos, G. Economakos, 2008, 2008 8th IEEE International Conference on BioInformatics and BioEngineering.

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

Dimitrios Soudris, Efstathios Sotiriou-Xanthopoulos, George Economakos, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Using high-level synthesis to build memory and datapath optimized DSP accelerators

Dionysios I. Reisis, Dionysios Diamantopoulos, George Economakos, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A cache based stack folding technique for high performance Java processors

George Economakos, Kiamal Pekmestzi, Isidoros Sideris, 2006, JTRES '06.

Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies

Harry Sidiropoulos, George Economakos, Christoforos E. Economakos, 2013, 2013 19th International Conference on Automation and Computing.

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2013, TODE.

AGENDA: an attribute grammar driven environment for the design automation of digital systems

George K. Papakonstantinou, Panayiotis Tsanakas, George Economakos, 1998, Proceedings Design, Automation and Test in Europe.

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Efficient C level hardware design for floating point biomedical DSP applications

Harry Sidiropoulos, George Economakos, Christoforos E. Economakos, 2013, 13th IEEE International Conference on BioInformatics and BioEngineering.

Performance improvements in a modern hardware design environment for control applications

George Economakos, Christoforos Economakos, Maria Tzamtzi, 2015, 2015 IEEE International Conference on Industrial Technology (ICIT).

A Reconfigurable Arithmetic Data-path Based On Regular Interconnection

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2016, TECS.

High Performance and Area Efficient Flexible

Dimitrios Soudris, Sotirios Xydis, George Economakos, 2011 .

An attribute grammar approach to high-level automated hardware synthesis

George K. Papakonstantinou, Panayiotis Tsanakas, George Economakos, 1995, Inf. Softw. Technol..

Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs

George K. Papakonstantinou, Panayiotis Tsanakas, George Economakos, 1998, SAC '98.

Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis

Sotirios Xydis, George Economakos, S. Xydis, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A Process-based Reconfigurable SystemC Module for simulation speedup

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2013, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

An architectural exploration framework for efficient FPGA implementation of PLC programs

George Economakos, Christoforos Economakos, 2009, 2009 17th Mediterranean Conference on Control and Automation.

Refinement and Property Checking in High-Level Synthesis using Attribute Grammars

George K. Papakonstantinou, George Economakos, G. Papakonstantinou, 1999, CHARME.

An instruction set extension for java bytecodes translation acceleration

Kiamal Z. Pekmestzi, George Economakos, Isidoros Sideris, 2008, 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation.

Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology

George Economakos, G. Economakos, 2009, 2009 17th European Signal Processing Conference.

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology

Angelos Amditis, Nikolaos K. Uzunoglu, George Economakos, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Design and experimentation with low-power morphable multipliers

Dimitrios Soudris, Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Systematic Design and Evaluation of Reconfigurable Arithmetic Components in the Deep submicron Domain

Sotirios Xydis, George Economakos, Dimitris Bekiaris, 2014, J. Circuits Syst. Comput..

Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic

Kiamal Z. Pekmestzi, George Economakos, Isidoros Sideris, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A Comparative Study of IEEE 802.11p Physical Layer Coding Schemes and FPGA Implementation for Inter Vehicle Communications

Angelos Amditis, Nikolaos K. Uzunoglu, George Economakos, 2013 .

A formal method for hardware design using attribute grammars

George K. Papakonstantinou, George Economakos, G. Papakonstantinou, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Extending an embedded RISC microprocessor for efficient translation based Java execution

Kiamal Z. Pekmestzi, George Economakos, Isidoros Sideris, 2009, Microprocess. Microsystems.

A mixed style architecture for low power multipliers based on a bypass technique

George Economakos, Kiamal Pekmestzi, Dimitris Bekiaris, 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Run-time reconfigurable solutions for adaptive control applications

Sotirios Xydis, George Economakos, Christoforos E. Economakos, 2007, ICINCO-SPSMC.

Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures

Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos, 2015, ARC.

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

Iraklis Anagnostopoulos, Dimitrios Soudris, Alexandros Bartzas, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Building embedded DSP applications in a Java modeling framework

Kiamal Z. Pekmestzi, George Economakos, Isidoros Sideris, 2007, 2007 15th European Signal Processing Conference.

Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL

Nectarios Koziris, Theodore Andronikos, George K. Papakonstantinou, 1997, HPCN Europe.

Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks

Dimitrios Soudris, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, 2014, PARMA-DITAM '14.

Lowpower design of multipliers using a full-adder isolation technique

George Economakos, Konstantinos Anagnostopoulos, K. Anagnostopoulos, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Dimitrios Soudris, Kostas Siozios, George Economakos, 2009, 2009 16th International Conference on Digital Signal Processing.

High-Speed Pipeline Implementation of Radix-2 DIF Algorithm

George Economakos, Kiamal Pekmestzi, Paul Bougas, 2007 .

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

Using advanced FPGA SoC technologies for the design of industrial control applications

George Economakos, Christoforos E. Economakos, George Kiokes, 2015, 2015 6th International Conference on Information, Intelligence, Systems and Applications (IISA).

A multi-lingual synthesis and verification environment

George K. Papakonstantinou, Stergios Stergiou, George Economakos, 2001, Proceedings Euromicro Symposium on Digital Systems Design.

A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis

Sotirios Xydis, George Economakos, S. Xydis, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching

Kiamal Z. Pekmestzi, Dimitrios Soudris, Sotirios Xydis, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

High-level synthesis with coarse grain reconfigurable components

Sotirios Xydis, George Economakos, S. Xydis, 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

Design and implementation of an OFDM system for vehicular communications with FPGA technologies

Angelos Amditis, Nikolaos K. Uzunoglu, George Economakos, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Optimal automatic hardware synthesis for signal processing algorithms

Nectarios Koziris, Theodore Andronikos, George K. Papakonstantinou, 1997, Proceedings of 13th International Conference on Digital Signal Processing.

Comparison of OpenCL based design for a medical device on heterogeneous architectures with CPU, GPU and FPGA

George Economakos, Efthymia Kazakou, 2015, Panhellenic Conference on Informatics.

Construction of dual mode components for reconfiguration aware high-level synthesis

Dimitrios Soudris, Sotirios Xydis, George Economakos, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A design methodology for high-performance and low-leakage fixed-point transpose FIR filters

Kiamal Z. Pekmestzi, Sotirios Xydis, George Economakos, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Hardware compilation using attribute grammars

Kiamal Z. Pekmestzi, George K. Papakonstantinou, Panayiotis Tsanakas, 1997, CHARME.

An open system for ECG telemedicine and telecare

A. Thanos, George K. Papakonstantinou, George Economakos, 1998, Computers in Cardiology 1998. Vol. 25 (Cat. No.98CH36292).

Reliability Breakdown Analysis of an MP-SoC platform due to Interconnect Wear-out

Dimitrios Soudris, Antonis Papanikolaou, George Economakos, 2009 .

New Systolic And Low Latency Parallel FIR Filter Schemes

Paraskevas Kalivas, Kiamal Z. Pekmestzi, George Economakos, .