J. A. Lopez

Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions

Tom J. Kazmierski, Ginés Doménech, J. A. Lopez, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Analysis of limit cycles by means of affine arithmetic computer-aided tests

Octavio Nieto-Taladriz, Gabriel Caffarena, Carlos Carreras, 2004, 2004 12th European Signal Processing Conference.