Nancy Heylen

发表

In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

Chi Lim Tan, Simone Lavizzari, Pieter Blomme, 2017, 2017 IEEE International Memory Workshop (IMW).

Cost Comparison of Different TSV Implementation Options

Eric Beyne, Anne Jourdain, Andy Miller, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Integration of a templated directed self-assembly-based hole shrink in a short loop via chain

Roel Gronheid, Nancy Heylen, Boon Teik Chan, 2016 .

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

Peter De Bisschop, Christopher J. Wilson, Ming Mao, 2018, Advanced Lithography.

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora\textregistered LK HM

David De Roest, Nancy Heylen, Herbert Struyf, 2010 .

In-line Small-Spot X-Ray Fluorescence Assessment of Electroplating and Chemical Mechanical Polishing

Nancy Heylen, Isaac Mazor, G. Bottiglieri, 2006 .

Impact of line height on copper resistivity and interconnect RC delay: a geometry approach to reduce the size effect

Karen Maex, Nancy Heylen, Gerald Beyer, 2005 .

Advanced Organic Polymer for the Aggressive Scaling of Low-k Materials

Nancy Heylen, Larry Zhao, Gerald Beyer, 2011 .

Surface planarization of Cu and CuNiSn Micro-bumps embedded in polymer for below 20μm pitch 3DIC applications

Eric Beyne, Andy Miller, Nancy Heylen, 2016 .

"Hole-in-One TSV", a New Via Last Concept for High Density 3D-SOC Interconnects

Eric Beyne, Anne Jourdain, Andy Miller, 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

Eric Beyne, Mikael Detalle, Andy Miller, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

3D-SoC integration utilizing high accuracy wafer level bonding

Eric Beyne, Andy Miller, Nancy Heylen, 2016, 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).

Ruthenium metallization for advanced interconnects

Christopher J. Wilson, Christoph Adelmann, Nancy Heylen, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$-Based 1T1R CBRAM Cell

Malgorzata Jurczak, Nancy Heylen, Andrea Fantini, 2013, IEEE Transactions on Electron Devices.

3D stacking using bump-less process for sub 10 µm pitches

Eric Beyne, Anne Jourdain, Andy Miller, 2016, ECTC 2016.

Modelling the influence of pad bending on the planarization performance during CMP

Marc Heyns, Nancy Heylen, Marc Meuris, 1999 .

Atomic Layer Deposition of Ruthenium with TiN Interface for Sub-10 nm Advanced Interconnects beyond Copper.

Christopher J. Wilson, Philippe Roussel, Christoph Adelmann, 2016, ACS applied materials & interfaces.

Influence of absorbed water components on SiOCH low-k reliability

Guido Groeseneken, Karen Maex, Ivan Ciofi, 2008 .