Satoshi Shimamoto

Metrology of LER: influence of line-edge roughness (LER) on transistor performance

Atsuko Yamaguchi, Hiroki Kawada, Takashi Iizumi, 2004, SPIE Advanced Lithography.

High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

Junichi Sakano, Takayuki Oshima, Satoshi Shimamoto, 2011, 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs.