Saurabh Khandelwal

发表

Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper

Shyam Akashe, Vijay Singh Rathor, Saurabh Khandelwal, 2014 .

Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

Balwinder Raj, Saurabh Khandelwal, Vishal Gupta, 2015, 2015 5th Nirma University International Conference on Engineering (NUiCONE).

Development of 3T eDRAM gain cells for enhancing read margin and data retention

Shyam Akashe, Saurabh Khandelwal, Tarushree Varshney, 2016 .

Implementation of Low Power Flip Flop Design in Nanometer Regime

Shyam Akashe, Saurabh Khandelwal, Pooja Joshi, 2015, 2015 Fifth International Conference on Advanced Computing & Communication Technologies.

Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction

Balwinder Raj, Saurabh Khandelwal, Sushil Bhushan, 2012, BIC-TA.

FinFET Based 6T SRAM Cell Design: Analysis of Performance Metric, Process Variation and Temperature Effect

Balwinder Raj, Saurabh Khandelwal, Rohan Gupta, 2015 .

Design & Optimization of FinFET Based Schmitt Trigger Using Leakage Reduction Techniques

Shyam Akashe, Saurabh Khandelwal, Pawan Sharma, 2015, 2015 Fifth International Conference on Advanced Computing & Communication Technologies.

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

Jimson Mathew, Marco Ottavi, Vishal Gupta, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Impact of NBTI on 8T FinFET based SRAM cell

Saurabh Khandelwal, Vikas Mahor, Bharat Tripathi, 2017, 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE).

Modeling and Analysis of FinFET Based Schmitt Trigger with Stability Response and Gain-Bandwidth Product

Shyam Akashe, Saurabh Khandelwal, Pawan Sharma, 2015 .

Reducing Leakage Power for SRAM Design Using Sleep Transistor

Shyam Akashe, Sanjay Sharma, Saurabh Khandelwal, 2013 .

Threshold Voltage Control through Multiple Supply for Low Power IG-FinFET Circuit

Shyam Akashe, Saurabh Khandelwal, Pavan Shrivastava, 2013 .

Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology

Shyam Akashe, Saurabh Khandelwal, Neha Yadav, 2013, 2013 International Conference on Control, Computing, Communication and Materials (ICCCCM).

High Performance FinFET Based D Flip Flop Including Parameter Variation

Shyam Akashe, Saurabh Khandelwal, Pooja Joshi, 2015 .

Implementation of High Performance SRAM Cell Using Transmission Gate

Shyam Akashe, Saurabh Khandelwal, Joshika Sharma, 2015, 2015 Fifth International Conference on Advanced Computing & Communication Technologies.

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

Shyam Akashe, Saurabh Khandelwal, Vandna Sikarwar, 2013 .

FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain–Bandwidth Product Analysis

Shyam Akashe, Pawan Sharma, Saurabh Khandelwal, 2016, Wirel. Pers. Commun..

Design and Optimization of 6T FinFET SRAM in 45 nm Technology

Balwinder Raj, Saurabh Khandelwal, Rohan Gupta, 2016 .

Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL

Shyam Akashe, Saurabh Khandelwal, Pooja Joshi, 2015, J. Low Power Electron..

Implementation of leakage reduction techniques in finfet based 3T DRAM based at 45 nm technology

Balwinder Raj, Saurabh Khandelwal, Ravi Shrivastava, 2017, 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE).

COSINE MODULATED FILTER-BANK TRANSMULTIPLEXER USING

Saurabh Khandelwal, Narendra Singh, 2013 .

Supply Voltage Minimization Techniques for SRAM Leakage Reduction

Shyam Akashe, Sanjay Sharma, Saurabh Khandelwal, 2012 .

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

Shyam Akashe, Saurabh Khandelwal, Neha Yadav, 2013 .

Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique

Shyam Akashe, Saurabh Khandelwal, Abhishek Dixit, 2014 .

Reliability Assessment of Memristor based Gas Sensor Array

Marco Ottavi, Abusaleh M. Jabir, Eugenio Martinelli, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations

Marco Ottavi, Abusaleh M. Jabir, Eugenio Martinelli, 2021, 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Design Low Power High Performance 8 : 1 MUX using Transmission Gate Logic ( TGL )

Saurabh Khandelwal, S. Khandelwal, 2014 .