Eric N. Paton

Optimizing the target-to-wafer spacing for highly uniform PVD films

Eric N. Paton, Ray Pena, Jeff Morioka, 1999, Advanced Lithography.

Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi

Qi Xiang, Ming-Ren Lin, Eric N. Paton, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Silicides for the 65 nm Technology Node

Paul L. King, Paul R. Besser, Simon S.M. Chan, 2003 .