G. Notermans

A methodology for the ESD test reduction for complex devices

T. Smedes, T. Keller, D. Maksimovic, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

ESD protection for high-voltage CMOS technologies

T. Smedes, Z. Mrcarica, G. Notermans, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Designing HV active clamps for HBM robustness

T. Smedes, A. Heringa, F. Blanc, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Pitfalls when correlating TLP, HBM and MM testing

G. Notermans, P. De Jong, F. Kuper, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

28V ESD clamp in CMOS 40nm process

F. Neri, G. Notermans, G. Chowdary, 2012, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC).

High voltage resistant ESD protection circuitry for 0.5 /spl mu/m CMOS OTP/EPROM programming pin

G. Notermans, H.-U. Schroder, G. Van Steenwijk, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

Gate oxide protection and ggNMOSTs in 65 nm

T. Smedes, R. Stephan, Z. Mrcarica, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.