A. Somayaji

High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies

C. Duvvury, R. Cline, A. Jahanzeb, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application

C. Duvvury, B. Haroun, J. Lin, 2002, Digest. International Electron Devices Meeting,.