Atsushi Takahashi

发表

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan(Special Section on Discrete Mathematics and Its Applications)

Atsushi Takahashi, Tomonori Izumi, Yoji Kajitani, 1998 .

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Atsushi Takahashi, Yukihide Kohira, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Manufacturability-aware mask assignment in multiple patterning lithography

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Computational complexity analysis of set-bin-packing problem

Atsushi Takahashi, Tomonori Izumi, Yoji Kajitani, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Three-layer L-shaped Channel Routing Algorithm with Nets Sharing

Atsushi Takahashi, Tutomu Utagawa, 1999 .

A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization

Atsushi Takahashi, Yiqiang Sheng, A. Takahashi, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

Clustering based fast clock scheduling for light clock-tree

Atsushi Takahashi, Makoto Saitoh, Masaaki Azuma, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Receiving opportunity control used admission control scheme for wireless multi-hop networks

Nobuyoshi Komuro, Atsushi Takahashi, Tutomu Murase, 2010, International Conference on Computer and Communication Engineering (ICCCE'10).

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound

Atsushi Takahashi, Yukihide Kohira, Suguru Suehiro, 2009 .

A fast clock scheduling for peak power reduction in LSI

Atsushi Takahashi, Yukihide Kohira, Yosuke Takahashi, 2007, GLSVLSI '07.

Global routing by iterative improvements for two-layer ball grid array packages

Atsushi Takahashi, Yukiko Kubo, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A practical clock tree synthesis for semi-synchronous circuits

Atsushi Takahashi, Masahiko Toyonaga, Keiichi Kurokawa, 2000, ISPD '00.

A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound

Atsushi Takahashi, Yukihide Kohira, Suguru Suehiro, 2009, 2009 Asia and South Pacific Design Automation Conference.

Itanium2 32-way server system Architecture

Atsushi Takahashi, Takayuki Itoh, Shinichi Kawaguchi, 2003 .

Octilinear Routing Method with Congestion Relaxation by Slant Lines

Atsushi Takahashi, Yukihide Kohira, Kyosuke Shinoda, 2009 .

Clock period minimization of semi-synchronous circuits by gate-level delay insertion

Atsushi Takahashi, Yoji Kajitani, Tomoyuki Yoda, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization

Atsushi Takahashi, Yukihide Kohira, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

Atsushi Takahashi, Yoji Kajitani, Kazunori Inoue, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement

Atsushi Takahashi, Shuichi Ueno, Yiqiang Sheng, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework

Atsushi Takahashi, Yukihide Kohira, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization

Atsushi Takahashi, Yiqiang Sheng, A. Takahashi, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Incremental Timing Budget Management in Programmable Systems

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004, ERSA.

Low area pipelined circuits by multi-clock cycle paths and clock scheduling

Atsushi Takahashi, Bakhtiar Affendi Rosdi, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees

Atsushi Takahashi, Masaaki Azuma, Makoto Saitoh, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A fast process variation and pattern fidelity aware mask optimization algorithm

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Improvement of Clock Scheduling Method in Consideration of Clock Tree Length

Atsushi Takahashi, Hajime Yamazaki, 2004 .

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An any-angle routing method using quasi-Newton method

Atsushi Takahashi, Yukihide Kohira, 2012, 17th Asia and South Pacific Design Automation Conference.

A Length Matching Routing Algorithm for Set-Pair Routing Problem

Atsushi Takahashi, Yuta Nakatani, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Internal information network device for a rail vehicle

Atsushi Takahashi, Shinsuke Watanabe, Yasuyuki Miyajima, 2009 .

A-3-4 Optimal Register Merging Method after Register Relocation in Semi-Synchronous Framework

Atsushi Takahashi, Yukihide Kohira, 2006 .

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Air-pressure-model-based fast algorithms for general floorplan

Atsushi Takahashi, Tomonori Izumi, Yoji Kajitani, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

755 Development of fuzzy inference spinning machine with Al alloy

Atsushi Takahashi, Kazumasa Kobayashi, Shoichiro Yoshihara, 2009 .

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems

Chikaaki Kodama, Atsushi Takahashi, Yukihide Kohira, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Hierarchical Cluster Analysis of Dense GNSS Data in Taiwan

Atsushi Takahashi, Manabu Hashimoto, Jyr-Ching Hu, 2018 .

Dawn of computer-aided design: from graph-theory to place and route

Atsushi Takahashi, 2013, ISPD '13.

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography

Chikaaki Kodama, Atsushi Takahashi, Tomomi Matsui, 2014, ISAAC.

2-SAT based linear time optimum two-domain clock skew scheduling

Atsushi Takahashi, Yukihide Kohira, Y. Kohira, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Effective two-dimensional pattern generation for self-aligned double patterning

Chikaaki Kodama, Atsushi Takahashi, Takeshi Ihara, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Improvement of Clustering Based Clock Scheduling Method

Atsushi Takahashi, Yukihide Kohira, Yuichi Sunahashiri, 2006 .

A global routing method for 2-layer ball grid array packages

Atsushi Takahashi, Yukiko Kubo, 2005, ISPD '05.

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits

Atsushi Takahashi, Bakhtiar Affendi Rosdi, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages

Atsushi Takahashi, Yoichi Tomioka, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Message from the Editor-in-Chief

Atsushi Takahashi, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages

Atsushi Takahashi, Yukiko Kubo, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages

Atsushi Takahashi, Yoichi Tomioka, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Monotonic parallel and orthogonal routing for single-layer ball grid array packages

Atsushi Takahashi, Yoichi Tomioka, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Mixed Searching and Proper-Path-Width

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1991, Theor. Comput. Sci..

Network-Flow Based Delay-Aware Circuit Partitioning Algorithm

Atsushi Takahashi, Masato Inagi, Kengo R. Azegami, 2002 .

portable electronic device and method for controlling a portable electronic device

Atsushi Takahashi, Norio Ishibashi, 2008 .

An overview of VLSI design automation and its future prospective

Atsushi Takahashi, 2010 .

A Fast Lithographic Mask Correction Algorithm (VLSI設計技術)

Atsushi Takahashi, Ahmed Awad, 2015 .

Clock period minimization method of semi-synchronous circuits by delay insertion

Atsushi Takahashi, Yukihide Kohira, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

A semi-monotonic routing method for fanin type Ball Grid Array packages

Atsushi Takahashi, Yoichi Tomioka, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages (デザインガイア2006--VLSI設計の新しい大地を考える研究会)

Atsushi Takahashi, Yoichi Tomioka, 2006 .

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages

Atsushi Takahashi, Yukihide Kohira, Yoichi Tomioka, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

MSA: mixed stochastic algorithm for placement with larger solution space (VLSI設計技術)

Atsushi Takahashi, Shuichi Ueno, Yiqiang Sheng, 2011 .

Atsushi Takahashi, Ting-Chi Wang, Shimpei Sato, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Practical Fast Clock-Schedule Design Algorithms

Atsushi Takahashi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements

Atsushi Takahashi, Bakhtiar Affendi Rosdi, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Semi-Synchronous Clock Tree Construction Under Synchronous Circuit Design Environment

Atsushi Takahashi, Seiichieo Ishijima, 2001 .

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework

Atsushi Takahashi, Yukihide Kohira, Shuhei Tani, 2009 .

Access control system for mobile node using a home agent

Atsushi Takahashi, Takashi Imaizumi, 2003 .

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution

Atsushi Takahashi, Shimpei Sato, Yuta Ukon, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Performance and reliability driven clock scheduling of sequential logic circuits

Atsushi Takahashi, Yoji Kajitani, Y. Kajitani, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Peel-the-box: a concept of switch-box routing and tractable problems

Atsushi Takahashi, Yoji Kajitani, 1992, Integr..

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning

Chikaaki Kodama, Atsushi Takahashi, Takeshi Ihara, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Yield-aware decomposition for LELE double patterning

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2014, Advanced Lithography.

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits

Atsushi Takahashi, Bakhtiar Affendi Rosdi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

Atsushi Takahashi, Yoji Kajitani, Kazunori Inoue, 1997, ICCAD 1997.

A Schedule Clock Tree Routing Algorithm for Minimum Effective Clock Skew

Makoto Saito, Atsushi Takahashi, Keishi Sakanushi, 1999 .

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework

Atsushi Takahashi, Yukihide Kohira, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages

Atsushi Takahashi, Yoichi Tomioka, 2008, 2008 Asia and South Pacific Design Automation Conference.

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution

Atsushi Takahashi, Shimpei Sato, Yuta Ukon, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Clock Tree Construction Method Under Delay Variations

Atsushi Takahashi, Masayuki Iguchi, 2006 .

Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2016 .

RRA-based multi-objective optimization to mitigate the worst cases of placement

Atsushi Takahashi, Shuichi Ueno, Yiqiang Sheng, 2011, 2011 9th IEEE International Conference on ASIC.

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2015, The 20th Asia and South Pacific Design Automation Conference.

Partition, Packing and Clock Distribution: A New Paradigm of Physical Design

Atsushi Takahashi, Yoji Kajitani, Shigetoshi Nakatake, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Localization concept of re-decomposition area to fix hotspots for LELE process

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2014, Advanced Lithography.

Yield-aware mask assignment using positive semi-definite relaxation in LELECUT triple patterning

Chikaaki Kodama, Shigeki Nojima, Atsushi Takahashi, 2015, Advanced Lithography.

Three-dimensional digital entity magnifying glass system incorporating three-dimensional visual training functions

Atsushi Takahashi, 2005 .

Optimal integer delay budgeting on directed acyclic graphs

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Single-Layer Trunk Routing Using Minimal 45-Degree Lines

Atsushi Takahashi, Yukihide Kohira, Kyosuke Shinoda, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Delay variation tolerant clock scheduling for semi-synchronous circuits

Atsushi Takahashi, H. Matsumura, A. Takahashi, 2001, Asia-Pacific Conference on Circuits and Systems.

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimization of delay insertion in clock period improvement in general-synchronous framework

Atsushi Takahashi, Yukihide Kohira, Shuhei Tani, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Detailed-routability of FPGAs with extremal switch-block structures

Atsushi Takahashi, Yoji Kajitani, Yasuhiro Takashima, 1996, Proceedings ED&TC European Design and Test Conference.

Circuit Modification Method of Semi-Synchronous Circuits with Retiminig

Atsushi Takahashi, Yukihide Kohira, Eigo Kamibayashi, 2005 .

Technical Tour to Mishima Mill, Taio Paper Mfg. Co., Ltd./Tour to Handmade Paper mill

Atsushi Takahashi, Shoji Fukamachi, 1979 .

Comparison among various synthesis methods on semi - synchronous framework

Atsushi Takahashi, Seiichiro Ishijima, Tetsuaki Utsumi, 2001 .

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern

Chikaaki Kodama, Atsushi Takahashi, Takeshi Ihara, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Optimal integer delay-budget assignment on directed acyclic graphs

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

CAFE router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles

Atsushi Takahashi, Yukihide Kohira, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

B-21-6 Unidirectional Flow Property aware Performance Improvement in Wireless Multi-hop Network

Nobuyoshi Komuro, Atsushi Takahashi, Shiro Sakata, 2009 .

Minimal acyclic forbidden minors for the family of graphs with bounded path-width

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1994, Discret. Math..

Fast EUV lithography simulation using convolutional neural network

Atsushi Takahashi, Hiroyoshi Tanabe, Shimpei Sato, 2021, Journal of Micro/Nanopatterning, Materials, and Metrology.

Fast 3D lithography simulation by convolutional neural network

Atsushi Takahashi, Shimpei Sato, Hiroyoshi Tanabe, 2021 .

2-Stage Simulated Annealing with Crossover Operator for 3 D-Packing Volume Minimization

Atsushi Takahashi, Shuichi Ueno, S. Ueno, 2012 .

Rip-up and Reroute based Routing Algorithm for Self-Aligned Double Patterning

Chikaaki Kodama, Atsushi Takahashi, Takeshi Ihara, 2015 .

Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1995 .

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm

Atsushi Takahashi, Yoji Kajitani, Masato Inagi, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling

Atsushi Takahashi, Masahiko Toyonaga, Takuya Yasui, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Cost-radius balanced spanning/Steiner trees

Atsushi Takahashi, Yoji Kajitani, Y. Kajitani, 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

On the Proper-Path-Decomposition of Trees

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1995 .

Optimal Integer Delay-Budget Assignment on

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004 .

Universal Graphs for Graphs with Bounded Path-Width

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1995 .