David M. Bull

发表

GeST: An Automatic Framework For Generating CPU Stress-Tests

Shidhartha Das, Yiannakis Sazeides, Paul N. Whatmough, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Selective time borrowing for DSP pipelines with hybrid voltage control loop

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2012, 17th Asia and South Pacific Design Automation Conference.

A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation

Shidhartha Das, David M. Bull, Ganesh S. Dasika, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Error-resilient low-power DSP via path-delay shaping

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Hybrid circuit and algorithmic timing error correction for low-power robust DSP accelerators

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster

Shidhartha Das, Paul N. Whatmough, Zacharias Hadjilambrou, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"

David Blaauw, Krisztián Flautner, Shidhartha Das, 2011, IEEE J. Solid State Circuits.

A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation

David Blaauw, Krisztián Flautner, Shidhartha Das, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation

David Blaauw, Krisztián Flautner, Shidhartha Das, 2011, IEEE Journal of Solid-State Circuits.

A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation

Shidhartha Das, David M. Bull, Ganesh S. Dasika, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

DVFS in loop accelerators using BLADES

Scott A. Mahlke, Shidhartha Das, Kevin Fan, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

David Blaauw, Shidhartha Das, Sanjay Pant, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Addressing design margins through error-tolerant circuits

David Blaauw, Krisztián Flautner, Shidhartha Das, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A robust FIR filter with in situ error detection

Izzat Darwazeh, Shidhartha Das, Paul N. Whatmough, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2014, IEEE Journal of Solid-State Circuits.

Error-Resilient Design Techniques for Reliable and Dependable Computing

Shidhartha Das, Paul N. Whatmough, David M. Bull, 2014, IEEE Transactions on Device and Materials Reliability.

A 0.6V all-digital body-coupled wakeup transceiver for IoT applications

Shidhartha Das, Yiannis Andreopoulos, Paul N. Whatmough, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

Shidhartha Das, Paul N. Whatmough, Zacharias Hadjilambrou, 2017, IEEE Journal of Solid-State Circuits.

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

David M. Bull, S. Kalaiselvan, D.T. Blaauw, 2009, IEEE Journal of Solid-State Circuits.