Guy Lemieux

发表

An improved "soft" eFPGA design and implementation strategy

Guy Lemieux, Resve A. Saleh, Victor Aken Ova, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

Guy Lemieux, Aaron Severance, G. Lemieux, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Automated Space/Time Scaling of Streaming Task Graph pdf

Guy Lemieux, Hossein Omidian, G. Lemieux, 2016, ArXiv.

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

Guy Lemieux, David Grant, Graeme Smecher, 2009, 2009 International Conference on Field-Programmable Technology.

Logic block clustering of large designs for channel-width constrained FPGAs

Guy Lemieux, Marvin Tom, G. Lemieux, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Modular SRAM-Based Binary Content-Addressable Memories

Guy Lemieux, Ameer Abdelhadi, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

DropBack: Continuous Pruning During Training pdf

Guy Lemieux, Mieszko Lis, Maximilian Golub, 2018, ArXiv.

Congestion Estimation and Localization in FPGAs : A Visual Tool for Interconnect Prediction

Guy Lemieux, Darius Chiu, David Yeager, 2007 .

An efficient FPGA overlay for portable custom instruction set extensions

Guy Lemieux, Dirk Koch, Christian Beckhoff, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions

Guy Lemieux, Johnny Tsung Lin Ho, 2009, FPGA '09.

Exploring automated space/time tradeoffs for OpenVX compute graphs

Guy Lemieux, Hossein Omidian, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Full Deep Neural Network Training On A Pruned Weight Budget

Guy Lemieux, Mieszko Lis, Maximilian Golub, 2018, MLSys.

Design of interconnection networks for programmable logic

Guy Lemieux, David A. Lewis, D. Lewis, 2003 .

Rapid synthesis and simulation of computational circuits in an MPPA

Guy Lemieux, David Grant, Graeme Smecher, 2009, FPT.

VEGAS: soft vector processor with scratchpad memory

Guy Lemieux, Christopher Han-Yu Chou, Aaron Severance, 2011, FPGA '11.

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

Guy Lemieux, Mark R. Greenstreet, Paul Teehan, 2009, FPGA '09.

Vector processing as a soft-core CPU accelerator

Guy Lemieux, Jason Yu, Christopher Eagleston, 2008, FPGA '08.

Analytical Framework for Switch Block Design

Guy Lemieux, David M. Lewis, D. Lewis, 2002, FPL.

Routing algorithms for FPGAS with sparse intra-cluster routing crossbars

Guy Lemieux, Philip Brisk, Yehdhih Ould Mohammed Moctar, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration

Guy Lemieux, Hossein Omidian, 2019, HEART 2019.

Parallel FPGA placement based on individual LUT placement (abstract only)

Guy Lemieux, Chris C. Wang, 2012, FPGA '12.

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Guy Lemieux, Steven J. E. Wilton, Jeffrey B. Goeders, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Using sparse crossbars within LUT

Guy Lemieux, David M. Lewis, D. Lewis, 2001, FPGA '01.

VENICE: A Compact Vector Processor for FPGA Applications

Guy Lemieux, Aaron Severance, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Generating highly-routable sparse crossbars for PLDs

Guy Lemieux, David M. Lewis, Paul Leventis, 2000, FPGA '00.

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs

Guy Lemieux, Paolo Ienne, Philip Brisk, 2012, FPGA '12.

Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training

Guy Lemieux, Amin Ghasemazar, Mieszko Lis, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs

Guy Lemieux, Ameer Abdelhadi, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Energy Recovery from High-Frequency Clocks Using DC-DC Converters

Shahriar Mirabbasi, Guy Lemieux, Patrick R. Palmer, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

TputCache: High-frequency, multi-way cache for high-throughput FPGA applications

Guy Lemieux, Aaron Severance, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Scalable and deterministic timing-driven parallel placement for FPGAs

Guy Lemieux, Chris C. Wang, G. Lemieux, 2011, FPGA '11.

GlitchLess: an active glitch minimization technique for FPGAs

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2007, FPGA '07.

Replace: An incremental placement algorithm for field programmable gate arrays

Guy Lemieux, David Leong, G. Lemieux, 2009, 2009 International Conference on Field Programmable Logic and Applications.

A WCUlEWTED CASE

Guy Lemieux, 1988 .

Deep and narrow binary content-addressable memories using FPGA-based BRAMs

Guy Lemieux, Ameer Abdelhadi, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)

Guy Lemieux, Steven J. E. Wilton, Usman Ahmed, 2010, FPGA '10.

On two-step routing for FPGAS

Guy Lemieux, Stephen Dean Brown, Daniel Vranesic, 1997, ISPD '97.

Design and implementation of the NUMAchine multiprocessor

Guy Lemieux, Zeljko Zilic, Michael Stumm, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)

Guy Lemieux, Shao Lin Tang, 2015, FPGA.

Soft vector processors with streaming pipelines

Guy Lemieux, Aaron Severance, Hossein Omidian, 2014, FPGA.

Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs

Guy Lemieux, Hossein Omidian, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

Session details: Architecture

Guy Lemieux, G. Lemieux, 2008, Symposium on Field Programmable Gate Arrays.

TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW pdf

Guy Lemieux, Aaron Severance, Satwant Singh, 2019, ArXiv.

A Survey and Taxonomy of GALS Design Styles

Guy Lemieux, Mark R. Greenstreet, Paul Teehan, 2007, IEEE Design & Test of Computers.

Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations

Guy Lemieux, Ameer Abdelhadi, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Session details: Emerging Technologies

Guy Lemieux, 2006, FPGA '06.

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter

Shahriar Mirabbasi, Guy Lemieux, Patrick R. Palmer, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

FPGA defect tolerance: impact of granularity

Anthony J. Yu, Guy Lemieux, G. Lemieux, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

ZUMA: An Open FPGA Overlay Architecture

Guy Lemieux, Alexander Brant, G. Lemieux, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Session details: FPGA architectures and circuits

Guy Lemieux, 2005, FPGA '05.

GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering

Guy Lemieux, Steven J. E. Wilton, Julien Lamoureux, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Accelerator compiler for the VENICE vector processor

Guy Lemieux, Satnam Singh, Aaron Severance, 2012, FPGA '12.

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Shahriar Mirabbasi, Guy Lemieux, Edmund Lee, 2006, 2006 IEEE International Conference on Field Programmable Technology.

PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

Guy Lemieux, Xiao Dong, G. Lemieux, 2009, 2009 International Conference on Field-Programmable Technology.

Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew

Guy Lemieux, Aaron Severance, Ameer Abdelhadi, 2012, 2012 International Conference on Field-Programmable Technology.

Circuit design of routing switches

Guy Lemieux, David M. Lewis, D. Lewis, 2002, FPGA '02.

PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters

Guy Lemieux, Johnny Tsung Lin Ho, 2008, 2008 International Conference on Field-Programmable Technology.

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Guy Lemieux, Philip Brisk, Yehdhih Ould Mohammed Moctar, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Directional and single-driver wires in FPGA interconnect

Anthony J. Yu, Guy Lemieux, Marvin Tom, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs

Guy Lemieux, Marvin Tom, David Leong, 2006, ICCAD.

Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)

Guy Lemieux, Steven J. E. Wilton, Usman Ahmed, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route

Guy Lemieux, David Grant, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Guy Lemieux, David Grant, G. Lemieux, 2008, TRETS.

Vector Processing as a Soft Processor Accelerator

Guy Lemieux, Christopher Han-Yu Chou, Jason Yu, 2009, TRETS.

A Case for Soft Vector Processors in FPGAs

Guy Lemieux, Jason Yu, 2007, 2007 International Conference on Field-Programmable Technology.

Extreme parallel architectures for the masses

Guy Lemieux, Tarek A. El-Ghazawi, 2008, FPGA '08.

The NUMAchine multiprocessor

Guy Lemieux, Tarek S. Abdelrahman, Zeljko Zilic, 2000, Proceedings 2000 International Conference on Parallel Processing.

Real-time object detection in software with custom vector instructions and algorithm changes

Guy Lemieux, Joe Edwards, 2017, 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Modular Switched Multiported SRAM-Based Memories

Guy Lemieux, Ameer Abdelhadi, 2016, ACM Trans. Reconfigurable Technol. Syst..

A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements

Guy Lemieux, David Grant, Chris Wang, 2011, FPGA '11.

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

Guy Lemieux, David Grant, Scott Chin, 2006, 2006 International Conference on Field Programmable Logic and Applications.

A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid

Shahriar Mirabbasi, Guy Lemieux, Patrick R. Palmer, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

VENICE: A compact vector processor for FPGA applications

Guy Lemieux, Aaron Severance, 2012, 2012 International Conference on Field-Programmable Technology.

Estimating reliability and throughput of source-synchronous wave-pipelined interconnect

Guy Lemieux, Mark R. Greenstreet, Paul Teehan, 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

System-on-Chip: Reuse and Integration

Shahriar Mirabbasi, Guy Lemieux, Alan J. Hu, 2006, Proceedings of the IEEE.

Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor

Guy Lemieux, Ameer Abdelhadi, Shao Lin Tang, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop

Guy Lemieux, Jonathan Rose, 2011, FPGA '11.

Rapid Overlay Builder for Xilinx FPGAs

Guy Lemieux, Dirk Koch, Michael Xi Yue, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories

Guy Lemieux, Lesley Shannon, Ameer Abdelhadi, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Guy Lemieux, Aaron Severance, Joe Edwards, 2015, FPGA.

Modular multi-ported SRAM-based memories

Guy Lemieux, Ameer Abdelhadi, 2014, FPGA.