P. Larsson-Edefors

Optimising a high-speed serial/parallel sum-of-products hardware structure with respect to bus utilisation

P. Larsson-Edefors, 1995 .

A 200-MHz CMOS bit-serial neural network

P. Larsson-Edefors, C. Svensson, H.O. Johansson, 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.