Gao-Ming Du

Prototype design of cluster-based homogeneous Multiprocessor System-on-Chip

Luo-Feng Geng, Duo-Li Zhang, Ming-Lun Gao, 2009, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication.

DReNoC: A dynamically reconfigurable computing system based on network-on-chip

Luo-Feng Geng, Duo-Li Zhang, Ming-Lun Gao, 2009, 2009 IEEE 8th International Conference on ASIC.

Design of an on-line configurable traffic generator for NoC

Luo-Feng Geng, Duo-Li Zhang, Ming-Lun Gao, 2009, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication.

Fractional-pel motion compensation interpolation architecture based on parallel FIR systolic arrays for H.264/AVC

Duo-Li Zhang, Ming-Lun Gao, Gao-Ming Du, 2008, 2008 2nd International Conference on Anti-counterfeiting, Security and Identification.

A novel VLSI architecture of lum interpolator of H.264 decoder

Duo-Li Zhang, Ming-Lun Gao, Gao-Ming Du, 2009, 2009 IEEE 8th International Conference on ASIC.

Design of a Hierarchy-Bus Based MPSoC on FPGA

Ming-Lun Gao, Ning Hou, Wei Zhang, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

An improved decoding method of coeff_token element for H.264 CAVLC decoder

Duo-Li Zhang, Gao-Ming Du, Yu-Kun Song, 2009, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication.

Design of heterogeneous MPSoC on FPGA

Wei Zhang, Ning Hou, Duo-Li Zhang, 2007, 2007 7th International Conference on ASIC.

A 4×4 pipelined intra frame decoder for H.264

Duo-Li Zhang, Ming-Lun Gao, Gao-Ming Du, 2009, 2009 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication.