Pieter Weckx

发表

40nm SiONプロセスにおけるランダムテレグラフノイズ複合欠陥モデルを用いた回路解析手法 (ディペンダブルコンピューティング) -- (デザインガイア2016 : VLSI設計の新しい大地)

Ben Kaczer, 藪内美智太郎, 大島梓, 2016 .

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model

Rudy Lauwereins, Liesbet Van der Perre, Francky Catthoor, 2012, DSD.

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes

Rudy Lauwereins, Liesbet Van der Perre, Francky Catthoor, 2014, 2014 17th Euromicro Conference on Digital System Design.

Accuracy of Quasi-Monte Carlo technique in failure probability estimations

Francky Catthoor, Dimitrios Soudris, Pieter Weckx, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Francky Catthoor, Dimitrios Soudris, Dimitrios Rodopoulos, 2014, IEEE Transactions on Device and Materials Reliability.

SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes

Julien Ryckaert, Pieter Weckx, Anshul Gupta, 2019, IEEE Electron Device Letters.

Mitigation of Sense Amplifier Degradation Using Skewed Design

Said Hamdioui, Mottaqiallah Taouil, Pieter Weckx, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7

Wim Dehaene, Praveen Raghavan, Pieter Weckx, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

BTI reliability from planar to FinFET nodes: Will the next node be more or less reliable?

Rudy Lauwereins, Liesbet Van der Perre, Francky Catthoor, 2014 .

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2019, Advanced Lithography.

Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability

Guido Groeseneken, Jacopo Franco, Ben Kaczer, 2014, 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).

Comparative BTI analysis for various sense amplifier designs

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Mitigation of sense amplifier degradation using input switching

Francky Catthoor, Wim Dehaene, Said Hamdioui, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

The defect-centric perspective of device and circuit reliability — From individual defects to circuits

Francky Catthoor, Dimitri Linten, Philippe Roussel, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Comparative BTI impact for SRAM cell and sense amplifier designs

Wim Dehaene, Said Hamdioui, Mottaqiallah Taouil, 2015 .

40nm SiONプロセスにおけるランダムテレグラフノイズ複合欠陥モデルを用いた回路解析手法 (VLSI設計技術) -- (デザインガイア2016 : VLSI設計の新しい大地)

Ben Kaczer, 藪内美智太郎, 大島梓, 2016 .

On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs

Ben Kaczer, Pieter Weckx, Petr Pfeifer, 2014, 2014 15th Latin American Test Workshop - LATW.

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

Jie Ding, A. Asenov, Naoto Horiguchi, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7

Wim Dehaene, Praveen Raghavan, Pieter Weckx, 2017, Advanced Lithography.

Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor

Wim Dehaene, Pieter Weckx, Nele Reynders, 2012, PATMOS.

Optimization of read and write performance of SRAMs for node 5nm and beyond

Pieter Weckx, Khaja Ahmad Shaik, Mohit Kumar Gupta, 2019, Advanced Lithography.

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

Said Hamdioui, Mottaqiallah Taouil, Praveen Raghavan, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations

Kazutoshi Kobayashi, Takashi Matsumoto, Ben Kaczer, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Comphy - A compact-physics framework for unified modeling of BTI

A. Subirats, Dimitri Linten, Geert Hellings, 2018, Microelectron. Reliab..

Characterization and simulation methodology for time-dependent variability in advanced technologies

Diederik Verkest, Francky Catthoor, Dimitri Linten, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model

Rudy Lauwereins, Liesbet Van der Perre, Francky Catthoor, 2012, 2012 15th Euromicro Conference on Digital System Design.

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Miguel Peón-Quirós, Alexandre Levisse, Pieter Weckx, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations

Ben Kaczer, Georges Gielen, Bertrand Parvais, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Physical-based RTN modeling of ring oscillators in 40-nm SiON and 28-nm HKMG by bimodal defect-centric behaviors

Kazutoshi Kobayashi, Hidetoshi Onodera, Takashi Matsumoto, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

BTI analysis for high performance and low power SRAM sense amplifier designs

Said Hamdioui, Mottaqiallah Taouil, Praveen Raghavan, 2015 .

Coping with Time-dependent Variability by a Combined Design and Technology Co-optimization

Pieter Weckx, 2016 .

Self-heating-aware CMOS reliability characterization using degradation maps

Dimitri Linten, Jacopo Franco, Ben Kaczer, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7

Wim Dehaene, Praveen Raghavan, Pieter Weckx, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Backside power delivery as a scaling knob for future systems

Eric Beyne, Julien Ryckaert, Pieter Weckx, 2019, Advanced Lithography.

Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology

Francky Catthoor, Philippe Roussel, Guido Groeseneken, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Scaling CMOS beyond Si FinFET: an analog/RF perspective

Diederik Verkest, A. Vandooren, Geert Hellings, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Scaling of BTI reliability in presence of time-zero variability

Francky Catthoor, Guido Groeseneken, Jacopo Franco, 2014, 2014 IEEE International Reliability Physics Symposium.

Capturing true workload dependency of BTI-induced degradation in CPU components

Francky Catthoor, Dimitrios Soudris, Zeljko Zilic, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability

Francky Catthoor, Wim Dehaene, Said Hamdioui, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Impact and mitigation of SRAM read path aging

Francky Catthoor, Wim Dehaene, Said Hamdioui, 2018, Microelectron. Reliab..

Origins and implications of increased channel hot carrier variability in nFinFETs

Naoto Horiguchi, Aaron Thean, Philippe Roussel, 2015, 2015 IEEE International Reliability Physics Symposium.

Methodology for Application-Dependent Degradation Analysis of Memory Timing

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Comparative experimental analysis of time-dependent variability using a transistor test array

Dimitri Linten, Guido Groeseneken, Jacopo Franco, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

BTI analysis of SRAM write driver

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2015, 2015 10th International Design & Test Symposium (IDT).

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

Francky Catthoor, Guido Groeseneken, Said Hamdioui, 2014, IEEE Transactions on Device and Materials Reliability.

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

Said Hamdioui, Mottaqiallah Taouil, Francky Catthoor, 2019, 2019 IEEE European Test Symposium (ETS).

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology

Francky Catthoor, Philippe Roussel, Guido Groeseneken, 2015, 2015 IEEE International Reliability Physics Symposium.

Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The impact of process variation and stochastic aging in nanoscale VLSI

Francky Catthoor, Guido Groeseneken, Saman Kiamehr, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Experimental evidences and simulations of trap generation along a percolation path

A. Asenov, Naoto Horiguchi, Tibor Grasser, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Time-Efficient Modeling and Simulation of True Workload Dependency for BTI-Induced Degradation in Processor-Level Platform Specifications

Dimitrios Rodopoulos, Simone Corbetta, Pieter Weckx, 2019 .

Sense amplifier offset voltage analysis for both time-zero and time-dependent variability

Wim Dehaene, Said Hamdioui, Mottaqiallah Taouil, 2019 .

The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

Dimitri Linten, Philippe Roussel, Tibor Grasser, 2016 .

Device aging: A reliability and security concern

Abhijit Chatterjee, Francky Catthoor, Adit D. Singh, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Smart-array for pipelined BTI characterization

Diederik Verkest, Dimitri Linten, Guido Groeseneken, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

Francky Catthoor, Dimitri Linten, Philippe Roussel, 2018, Microelectron. Reliab..

Reliability aware simulation flow: From TCAD calibration to circuit level analysis

Asen Asenov, Naoto Horiguchi, Jacopo Franco, 2015, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Read path degradation analysis in SRAM

Francky Catthoor, Wim Dehaene, Said Hamdioui, 2016, 2016 21th IEEE European Test Symposium (ETS).

Degradation analysis of high performance 14nm FinFET SRAM

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier

Francky Catthoor, Said Hamdioui, Mottaqiallah Taouil, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

eSRAM Reliability: Why is it still not optimally solved?

Said Hamdioui, Mottaqiallah Taouil, Pieter Weckx, 2020, 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Analysis of advanced technology nodes and h-NA EUV introduction: a cost perspective

Geert Hellings, Julien Ryckaert, Pieter Weckx, 2021, Photomask Technology.

Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm

Naoto Horiguchi, Julien Ryckaert, Pieter Weckx, 2021 .

Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm

Francky Catthoor, Odysseas Zografos, Pieter Weckx, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies

Dimitri Linten, Geert Hellings, Jacopo Franco, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits

Francky Catthoor, Guido Groeseneken, Jacopo Franco, 2014, IEEE Transactions on Electron Devices.

Statistical Distribution of Defect Parameters

Jacopo Franco, Ben Kaczer, Pieter Weckx, 2014 .

BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors

Naoto Horiguchi, Dimitri Linten, Jacopo Franco, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).