D. Amparo

Experimental Investigation of ERSFQ Circuit for Parallel Multibit Data Transmission

J. Walter, T. V. Filippov, I. V. Vernik, 2017, 2017 16th International Superconductive Electronics Conference (ISEC).

Effects of Adaptive DC Biasing on Operational Margins in ERSFQ Circuits

A. Sahu, I. V. Vernik, O. A. Mukhanov, 2017, IEEE Transactions on Applied Superconductivity.

20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

D. Amparo, A. Kirichenko, D. Yohannes, 2007, IEEE Transactions on Applied Superconductivity.