Shihui Yin

发表

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Yandong Luo, Xiaoyu Sun, Shimeng Yu, 2019, IEEE Micro.

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory

Eriko Nurvitadhi, Shihui Yin, Shreyas K. Venkataramanaiah, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2018, 2018 IEEE Symposium on VLSI Technology.

A 1.06 μW smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yu Cao, Jae-sun Seo, Yang Liu, 2017, VLSIC 2017.

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

Mingoo Seok, Shihui Yin, Jae-Sun Seo, 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yu Cao, Minkyu Kim, Yang Liu, 2017, IEEE Journal of Solid-State Circuits.

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression

Sang Joon Kim, Jae-sun Seo, Shihui Yin, 2020, IEEE Transactions on Biomedical Circuits and Systems.

A 1.06 μW smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yu Cao, Minkyu Kim, Jae-sun Seo, 2019, 2017 Symposium on VLSI Circuits.

High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Shimeng Yu, Jae-sun Seo, Shihui Yin, 2019, IEEE Transactions on Electron Devices.

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2020, IEEE Journal of Solid-State Circuits.

2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning

Xiaoyu Sun, Shimeng Yu, Jae-Joon Kim, 2020, IEEE Solid-State Circuits Letters.

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Shihui Yin, Jae-Sun Seo, Bipin Rajendran, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 2.6 TOPS/W 16-Bit Fixed-Point Convolutional Neural Network Learning Processor in 65-nm CMOS

Shihui Yin, Jae-Sun Seo, Jae-sun Seo, 2020, IEEE Solid-State Circuits Letters.

A Novel Programming Method for Multilevel RRAM Based on Pulse Width Modulation

Ru Huang, Cheng Chen, Shihui Yin, 2013 .

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation

Sang Joon Kim, Shihui Yin, Jae-Sun Seo, 2019, 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC).

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM

Jae-sun Seo, Mingoo Seok, Shihui Yin, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration

Tushar Gupta, Minkyu Kim, Jae-sun Seo, 2019, 2019 53rd Asilomar Conference on Signals, Systems, and Computers.

Inference engine benchmarking across technological platforms from CMOS to RRAM

Xiaochen Peng, Xiaoyu Sun, Shimeng Yu, 2019, MEMSYS.

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

Mingoo Seok, Shihui Yin, Jae-Sun Seo, 2019, IEEE Solid-State Circuits Letters.

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation

Jae-sun Seo, Shihui Yin, Deepak Kadetotad, 2020, IEEE Journal of Solid-State Circuits.

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Jae-sun Seo, Shihui Yin, Bipin Rajendran, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks

Jae-sun Seo, Mingoo Seok, Deliang Fan, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design

Mingoo Seok, Shihui Yin, Jae-Sun Seo, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Minkyu Kim, Jae-sun Seo, Mingoo Seok, 2021, 2021 Symposium on VLSI Circuits.

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing

Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

The Sooner The Better: Investigating Structure of Early Winning Lottery Tickets

Mauricio J. Serrano, Jinwook Oh, Shihui Yin, 2019 .