V. N. Sekhar

发表

Active Silicon Interposer for Heterogeneous Integration: System Scaling and Cost Effectiveness

Surya Bhattacharya, Vivek Chidambaram, Jayabalan Jayasanker, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Heterogeneous Three-Layer TSV Chip Stacking Assembly With Moldable Underfill

C. T. Chong, V. N. Sekhar, S. L. Pei-Siang, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Antenna-in-Package Design Based on Wafer-Level Packaging With Through Silicon Via Technology

Rui Li, Bangtao Chen, Xiaoyue Bao, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Wafer level embedding technology for 3D wafer level embedded package

V. N. Sekhar, D. Kwong, V. Kripesh, 2009, 2009 59th Electronic Components and Technology Conference.

Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices

V. N. Sekhar, Cheng Jin, Bangtao Chen, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan)

Li Hong Yu, C. C. Kuo, Cheng Cheng Kuo, 2010, 2010 12th Electronics Packaging Technology Conference.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

A. Kumar, D. Pinjala, J. H. Lau, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A low stress bond pad design for low temperature solder interconnections on through silicon vias (TSVs)

D. Pinjala, R. Rajoo, Ling Xie, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-k Stack

A. Kumar, J. H. Lau, V. Kripesh, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material

V. N. Sekhar, V. S. Rao, G. Sharma, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Wafer level packaging of RF MEMS devices using TSV interposer technology

V. N. Sekhar, Justin See Toh, S. Fernando, 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).

Challenges and approaches of TSV thin die stacking on organic substrate

C. T. Chong, V. N. Sekhar, C. Choong, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

Influence of thickness on nanomechanical behavior of Black Diamond™ low dielectric thin films for interconnect and packaging applications

V. N. Sekhar, S. Balakumar, S. Yoon, 2009 .

Investigation of mechanical properties of black diamond tm (low-K) thin films for Cu/low-k interconnect applications

V. N. Sekhar, S. Balakumar, A. Tay, 2006, 2006 8th Electronics Packaging Technology Conference.

Embedding of 15um thin chip and passives in thin flexible substrate

V. N. Sekhar, Xiaowu Zhang, S. W. Ho, 2010, 2010 12th Electronics Packaging Technology Conference.

Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking

Siong Chiew Ong, V. N. Sekhar, C. Selvanayagam, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

A study on the mechanical behavior of the sputtered nickel thin films for UBM applications

V. N. Sekhar, A. Tay, R. Jayaganthan, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

6um Pitch High Density Cu-Cu Bonding for 3D IC Stacking

Ling Xie, Ser Choong Chong, Sunil Wickramanayaka, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Fractal analysis of intermetallic compounds in Sn–Ag, Sn–Ag–Bi, and Sn–Ag–Cu diffusion couples

V. N. Sekhar, V. Kripesh, A. Tay, 2006 .

Nanoindentation study of the sputtered Cu thin films for interconnect applications

V. N. Sekhar, V. Kripesh, A. Tay, 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

Heterogeneous System Level Integration Using Active Si Interposer

V. N. Sekhar, Wang Xiangyu, V. Chidambaram, 2019, IEEE Journal of the Electron Devices Society.

Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages

Khong Chee Houe, Lim Ying Ying, V. N. Sekhar, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Mechanical Characterization of Black Diamond (Low-k) Structures for 3D Integrated Circuit and Packaging Applications

V. N. Sekhar, 2012 .

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

John H. Lau, Xiaowu Zhang, Vempati Srinivasa Rao, 2010, Microelectron. Reliab..

Advanced System in Package Enabled by Wafer Level Heterogeneous Integration of Chiplets

V. N. Sekhar, T. Lim, V. S. Rao, 2022, 2022 International Electron Devices Meeting (IEDM).

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

Xiaowu Zhang, R. Murthy, W.H. Zhu, 2008, 2008 58th Electronic Components and Technology Conference.