Hiromasa Noda

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

Youji Idei, Katsuhiro Shimohigashi, Katsuyuki Sato, 1998 .

An 8.4ns Column-Access 1.6Gb/s/pin 512Mb DDR3 SDRAM with an 8:4 Multiplexed Data Transfer Scheme and Dual-Clock Latency Counter

Masayuki Nakamura, Takahiro Ito, Hitoshi Tanaka, 2006 .

A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs

Takeshi Sakata, Kyoko Murakami, Sadayuki Ohkuma, 2002 .

Significance of Charge Sharing in Causing Threshold Voltage Roll-Off in Highly Doped 0.1-μm Si MOSFETs and Its Suppression by Atomic Layer Doping(ALD)

Shinichiro Kimura, Hiromasa Noda, Kaori Nakamura, 1993 .

Significance of charge sharing in causing threshold voltage roll-off in highly doped 0.1-μm Si metal oxide semiconductor field effect transistors and its suppression by atomic layer doping

Shinichiro Kimura, Hiromasa Noda, Kaori Nakamura, 1994 .

A sub-0.1-/spl mu/m grooved gate MOSFET with high immunity to short-channel effects

Toru Toyabe, Shinichiro Kimura, Hiromasa Noda, 1993, Proceedings of IEEE International Electron Devices Meeting.

Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate

Toru Toyabe, Shinichiro Kimura, Hiromasa Noda, 1995 .