Yoshiaki Asao

A 17-ns 4-Mb CMOS DRAM

K. Numata, Munehiro Yoshida, Mitsuru Shimizu, 1991 .

WPM 3.7: A 1711s 4Mb CMOS DRAM Using Direct Bit-Line Sensing Technique

Takahiko Hara, Y. Saito, Munehiro Yoshida, 1991 .

A 17ns 4Mb CMOS DRAM Using Direct Bit-line Sensing Technique

Takahiko Hara, K. Numata, Munehiro Yoshida, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.