P.M. Kogge

Of Piglets and Threadlets: Architectures for Self-Contained, Mobile, Memory Programming

P.M. Kogge, P. Kogge, 2004, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04).

Comparing the Reliability of PLA and Custom Logic Implementations of a QCA Adder

P.M. Kogge, T.J. Dysart, 2008, 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems.

Redundancy in Multi-core Memory-Rich Application-Specific PIM Chips

P.M. Kogge, J.B. Brockman, 2006, International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06).

Some Initial Explorations into the Hierarchical Multi-core Chip Design Space for HPC Systems

P.M. Kogge, 2007, Innovative architecture for future generation high-performance processors and systems (iwia 2007).

An exploration of the technology space for multi-core memory/logic chips for highly scalable parallel systems

P.M. Kogge, 2005, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05).

Hardware/software codesign for video compression using the EXECUBE processing array

P.M. Kogge, M. Sheliga, E. Hsing-Mean Sha, 1997, Proceedings of the IEEE 1997 National Aerospace and Electronics Conference. NAECON 1997.

Pursuing a petaflop: point designs for 100 TF computers using PIM technologies

P.M. Kogge, J.B. Brockman, D.Z. Chen, 1996, Proceedings of 6th Symposium on the Frontiers of Massively Parallel Computation (Frontiers '96).