Swapnil Mhaske

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Ahsan Aziz, Swapnil Mhaske, Hojin Kee, 2017, Int. J. Reconfigurable Comput..

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation

Ahsan Aziz, Swapnil Mhaske, Hojin Kee, 2015, 2015 36th IEEE Sarnoff Symposium.

HIGH-THROUGHPUT FPGA QC-LDPC DECODER ARCHITECTURE FOR 5G WIRELESS

Swapnil Mhaske, Swapnil Mhaske, 2015 .

Link quality analysis in the presence of blockages for analog beamformed mm-wave channel

Ahsan Aziz, Malik Muhammad Usman Gul, Swapnil Mhaske, 2016, MILCOM 2016 - 2016 IEEE Military Communications Conference.

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R pdf

Ahsan Aziz, Swapnil Mhaske, Hojin Kee, 2015, ArXiv.

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA

Swapnil Mhaske, Hojin Kee, Tai Ly, 2014, 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP).

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

Ahsan Aziz, Swapnil Mhaske, Hojin Kee, 2015, 2015 IEEE 82nd Vehicular Technology Conference (VTC2015-Fall).

FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis

Swapnil Mhaske, Hojin Kee, Tai Ly, 2016, 2016 IEEE 37th Sarnoff Symposium.

Rate compatible IRA codes using row splitting for 5G wireless

Swapnil Mhaske, Predrag Spasojevic, Brennan Young, 2015, 2015 49th Annual Conference on Information Sciences and Systems (CISS).

A Blockage Model for the Open Area Mm-wave Device-to-Device Environment pdf

Swapnil Mhaske, Predrag Spasojevic, Ahsan Aziz, 2019, ArXiv.