Dhiraj K. Pradhan

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Fault-tolerant computer system design

Dhiraj K. Pradhan, D. Pradhan, 1996 .

Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits

Dhiraj K. Pradhan, Jimson Mathew, Mohamad Imran Bin Bandan, 2017, IEEE Transactions on Reliability.

Simultaneous Scheduling and Binding for Low Gate Leakage Nano-CMOS Datapath Circuit Behavioral Synthesis

Dhiraj K. Pradhan, Saraju P. Mohanty, Elias Kougianos, 2006 .

Pseudo parallel architecture for AES with error correction

Dhiraj K. Pradhan, Jimson Mathew, Yi Xin Su, 2008, 2008 IEEE International SOC Conference.

Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach

Dhiraj K. Pradhan, Florin Balasa, 2011 .

Secure Testable S-box Architecture for Cryptographic Hardware Implementation

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, Comput. J..

Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 International Symposium on Electronic System Design.

Performance of TCP over Wireless Networks

Dhiraj K. Pradhan, Nitin H. Vaidya, B. S. Bakshi, 1995 .

Technologies through Innovative Design

Dhiraj K. Pradhan, Luigi Carro, Costas Ar, 2009 .

Eco-friendly Computing and Communication Systems

Dhiraj K. Pradhan, Jimson Mathew, Priyadarshan Patra, 2012, Communications in Computer and Information Science.

IEEE High-Level Design Validation and Test Workshop

Dhiraj K. Pradhan, Hafizur Rahaman, J Matthew, 2006 .

Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Single error correctable bit parallel multipliers over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2009, IET Comput. Digit. Tech..

Introduction to design techniques for energy harvesting

Dhiraj K. Pradhan, Taskin Koçak, 2008, JETC.

A Fault-Diagnosis Technique for Closed Flow Networks.

Dhiraj K. Pradhan, K Matsui, 1980 .

Design of Reversible Finite Field Arithmetic Circuits with Error Detection

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

Dhiraj K. Pradhan, Costas Argyrides, Hamid R. Zarandi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)

Dhiraj K. Pradhan, Argyrides Costas, Zarandi Hamid, 2007 .

A multiprocessor network suitable for single-chip VLSI implementation

Dhiraj K. Pradhan, M. R. Samatham, 1984, ISCA 1984.

Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability

Dhiraj K. Pradhan, Debendra Das Sharma, D. Pradhan, 1996, J. Parallel Distributed Comput..

Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model

Dhiraj K. Pradhan, Fred J. Meyer, D. D. Sharma, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Complementary resistive switch based stateful logic operations using material implication: Design, Automation and Test in Europe Conference and Exhibition (DATE)

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2014, DATE 2014.

Scalability of binary deBruijn networks

Dhiraj K. Pradhan, Barun K. Kar, 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

Bit-serial generalized median filters

Dhiraj K. Pradhan, Barun K. Kar, Khadem M. Yusuf, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

Dhiraj K. Pradhan, Israel Koren, D. Pradhan, 1987, IEEE Transactions on Computers.

Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off

Dhiraj K. Pradhan, Nitin H. Vaidya, 1997, IEEE Trans. Computers.

Fault Tolerant Reversible Finite Field Arithmetic Circuits

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2008, 2008 14th IEEE International On-Line Testing Symposium.

A graph-structural approach for the generalization of data management systems

Dhiraj K. Pradhan, L. C. Chang, 1977, Inf. Sci..

Degradable agreement in the presence of Byzantine faults

Dhiraj K. Pradhan, Nitin H. Vaidya, 1993, [1993] Proceedings. The 13th International Conference on Distributed Computing Systems.

Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks

Dhiraj K. Pradhan, Vishram Mishra, Jimson Mathew, 2011, Int. J. Sens. Networks.

Cooperating diverse experts: a methodology to develop quality software for critical decision support systems

Dhiraj K. Pradhan, M. Hecht, H. Hecht, 1995, 1995 IEEE Aerospace Applications Conference. Proceedings.

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF $(2^{m})$

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

LPRAM: a low power DRAM with testability

Dhiraj K. Pradhan, Subhasis Bhattacharjee, 2004 .

2T2M memristor based TCAM cell for low power applications

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2011, Circuits Syst. Signal Process..

Yield modeling and optimization of large redundant RAMs

Dhiraj K. Pradhan, K. N. Ganapathy, A. D. Singh, 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.

Design of Single-Bit Fault-Tolerant Reversible Circuits

Dhiraj K. Pradhan, Ashutosh Kumar Singh, Masahiro Fujita, 2021, IEEE Design & Test.

Yield optimization in large RAM's with hierarchical redundancy

Dhiraj K. Pradhan, K. N. Ganapathy, A. D. Singh, 1991 .

Adaptive Checkpoint Interval Algorithm Considering Task Deadline and Lifetime Reliability for Real-Time System☆

Dhiraj K. Pradhan, Jimson Mathew, Subhasis Bhattacharjee, 2015 .

Dynamic Testing Strategy for Distributed Systems

Dhiraj K. Pradhan, Fred J. Meyer, 1989, IEEE Trans. Computers.

MODD for CF: a representation for fast evaluation of multiple-output functions

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

The hyper-deBruijn multiprocessor networks

Dhiraj K. Pradhan, Elango Ganesan, D. Pradhan, 1991, [1991] Proceedings. 11th International Conference on Distributed Computing Systems.

Fault-Tolerant Asynchronous Networks Using Read-Only Memories

Dhiraj K. Pradhan, 1978, IEEE Transactions on Computers.

Integrated Circuit Manufacturability: The Art of Process and Design Integration

Dhiraj K. Pradhan, J. Pineda de Gyvez, D. Pradhan, 1998 .

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})

Dhiraj K. Pradhan, Jimson Mathew, Biplab K. Sikdar, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Eco-friendly Computing and Communication Systems: International Conference, ICECCS 2012, Kochi, India, August 9-11, 2012. Proceedings

Dhiraj K. Pradhan, Jimson Mathew, Priyadarsan Patra, 2012 .

Organization and analysis of a gracefully-degrading interleaved memory system

Dhiraj K. Pradhan, Kewal K. Saluja, Gurindar S. Sohi, 1987, ISCA '87.

A hierarchical directory scheme for large-scale cache-coherent multiprocessors

Dhiraj K. Pradhan, Dominique Thiébaut, Yeong-Chang Maa, 1992, Proceedings Sixth International Parallel Processing Symposium.

Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement

Dhiraj K. Pradhan, Fabian Vargas, Costas Argyrides, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Computational analysis and comparison of reversible gates for design and test of logic circuits

Dhiraj K. Pradhan, Ashutosh Kumar Singh, A. Mohan, 2019, International Journal of Electronics.

GLFSR-a new test pattern generator for built-in-self-test

Dhiraj K. Pradhan, Mitrajit Chatterjee, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Flip-Trees: Fault-Tolerant Graphs with Wide Containers

Dhiraj K. Pradhan, Fred J. Meyer, D. Pradhan, 1988, IEEE Trans. Computers.

Fault detection and repair of DSC arrays through memristor sensing

Dhiraj K. Pradhan, Jimson Mathew, Yuamfam Yang, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Buffer assignment for data driven architectures

Dhiraj K. Pradhan, Savita Banerjee, Mitrajit Chatterjee, 1993, ICCAD.

Single Event Upset Detection and Correction

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2007, 10th International Conference on Information Technology (ICIT 2007).

Fault-tolerant computing : theory and techniques

Dhiraj K. Pradhan, Jacob A. Abraham, J. Abraham, 1986 .

RTRAM: reconfigurable and testable multi-bit RAM design

Dhiraj K. Pradhan, Nirmala R. Kamath, D. Pradhan, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2008, 2008 IEEE International SOC Conference.

Fault Tolerant Multiprocessor Systems

Gavin D. Holland, Dhiraj K. Pradhan, 2001 .

A Galois field-based logic synthesis with testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, IET Comput. Digit. Tech..

Static and adaptive location management in mobile wireless networks

Dhiraj K. Pradhan, Nitin H. Vaidya, P. Krishna, 1996, Comput. Commun..

Fault-Tolerant Asynchronous Networks

Dhiraj K. Pradhan, Sudhakar M. Reddy, 1973, IEEE Transactions on Computers.

The DeSyRe project: on-Demand System Reliability (invited paper)

Dhiraj K. Pradhan, Babak Falsafi, Christos-Savvas Bouganis, 2012 .

A novel pattern generator for near-perfect fault-coverage

Dhiraj K. Pradhan, Mitrajit Chatterjee, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Recent advances in verification, equivalence checking & SAT solvers

Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea, 2003, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

Introduction to SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2013 .

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2009, 2009 22nd International Conference on VLSI Design.

An application specific processor for implementing stack filters

Dhiraj K. Pradhan, Barun K. Kar, R. C. K. Kumar, 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

Recovery in Multicomputers with Finite Error Detection Latency

Dhiraj K. Pradhan, Nitin H. Vaidya, P. Krishna, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

DeSyRe: On-demand system reliability

Dhiraj K. Pradhan, Babak Falsafi, Christos-Savvas Bouganis, 2013, Microprocess. Microsystems.

BIT-based weighted mean filter

Dhiraj K. Pradhan, Barun K. Kar, Mitrajit Chatterjee, 1996, 1996 8th European Signal Processing Conference (EUSIPCO 1996).

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Performance issues in mobile wireless networks

Dhiraj K. Pradhan, Nitin H. Vaidya, Pravin Krishna, 1996 .

A novel framework for logic verification in a synthesis environment

Dhiraj K. Pradhan, Sudhakar M. Reddy, Wolfgang Kunz, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ATPG for Design Errors-Is It Possible?

Dhiraj K. Pradhan, Magdy S. Abadir, Scott Davidson, 2001, VTS.

Guest Editorial

Dhiraj K. Pradhan, Jimson Mathew, Rajat Subhra Chakraborty, 2017, ACM Trans. Embed. Comput. Syst..

Multiple Event Upsets Aware FPGAs Using Protected Schemes

Dhiraj K. Pradhan, Costas Argyrides, 2008, Fault-Tolerant Distributed Algorithms on VLSI Chips.

Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays

Dhiraj K. Pradhan, D. Pradhan, 1978, IEEE Transactions on Computers.

Asia South Pacific Design Automation Conference (ASPDAC)

Dhiraj K. Pradhan, Subhasis Bhattacharjee, 2004 .

Synthesis of initializable asynchronous circuits

Dhiraj K. Pradhan, Srimat T. Chakradhar, Rabindra K. Roy, 1994, Proceedings of 7th International Conference on VLSI Design.

Integrated software tools for the memory management of low-energy embedded signal processing systems

Dhiraj K. Pradhan, Florin Balasa, D. Pradhan, 2012, 2012 5th International Congress on Image and Signal Processing.

Low Cost C-Testable Finite Field Multiplier Architectures

Dhiraj K. Pradhan, Hafizur Rahaman, Jimson Mathew, 2014 .

A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability

Dhiraj K. Pradhan, Sandeep K. Gupta, D. Pradhan, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Roll-forward and rollback recovery: performance-reliability trade-off

Dhiraj K. Pradhan, Nitin H. Vaidya, 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

Error-Control Techniques for Logic Processors

Dhiraj K. Pradhan, Sudhakar M. Reddy, S. Reddy, 1972, IEEE Transactions on Computers.

VERILAT: verification using logic augmentation and transformations

Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee, 1996, Proceedings of International Conference on Computer Aided Design.

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems

Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis, 2014, J. Low Power Electron..

A fast and efficient strategy for submesh allocation in mesh-connected parallel computers

Dhiraj K. Pradhan, Debendra Das Sharma, 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

Initialization issues in the synthesis of asynchronous circuits

Dhiraj K. Pradhan, Srimat T. Chakradhar, Rabindra K. Roy, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

IEEE International On-Line Testing Symposium

Dhiraj K. Pradhan, Argyrides Costas, Vargas Fabian, 2008 .

Synthesis of initializable asynchronous circuits

Dhiraj K. Pradhan, Srimat T. Chakradhar, Rabindra K. Roy, 1996, IEEE Trans. Very Large Scale Integr. Syst..

The effect of memory-management policies on system reliability

Dhiraj K. Pradhan, N. S. Bowen, 1993 .

A Novel Soft Error Tolerant Low Power RAM Architecture

Dhiraj K. Pradhan, Luigi Carro, Argyrides Costas, 2007 .

EBIST: a novel test generator with built-in fault detection capability

Dhiraj K. Pradhan, Chunsheng Liu, Krish Chakraborty, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Mathematical framework for representing discrete functions as word-level polynomials

Dhiraj K. Pradhan, Maciej J. Ciesielski, Serkan Askar, 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems

Dhiraj K. Pradhan, 1991 .

ALowPower128-pt Implementation ofFFT/IFFT for HighPerformance Wireless Personal AreaNetworks

Dhiraj K. Pradhan, Jimson Mathew, Koushik Maharatna, 2006 .

Aliasing Probability for Multiple Input Signature Analyzer

Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky, 1990, IEEE Trans. Computers.

Providing Seamless Communications in Mobile Wireless Networks

Dhiraj K. Pradhan, Nitin H. Vaidya, Pravin Krishna, 1995 .

Signature analysis under a delay fault model

Dhiraj K. Pradhan, Jayashree Saxena, 1992, [1992] Proceedings The European Conference on Design Automation.

On the Hardware Reduction of z-Datapath of Vectoring CORDIC

Dhiraj K. Pradhan, Jimson Mathew, Koushik Maharatna, 2007, 2007 IEEE International Symposium on Circuits and Systems.

GASIM: a fast Galois field based simulator for functional model

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

Boolean satisfiability and EDA applications

Dhiraj K. Pradhan, Joao Marques-Silva, Ian G. Harris, 2009 .

Don''t Care Based Implications for Faster and Improved Verification

Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee, 2001 .

A cluster-based approach for routing in dynamic networks

Dhiraj K. Pradhan, Nitin H. Vaidya, Mainak Chatterjee, 1997, CCRV.

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Costas Argyrides, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Single Event Upset Detection and Correction

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2007 .

Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs

Dhiraj K. Pradhan, Argyrides Costas, S Demetriou, 2007 .

Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks

Dhiraj K. Pradhan, Jimson Mathew, Koushik Maharatna, 2011 .

Towards on-demand system reliability: software implemented fault tolerance and testing

Dhiraj K. Pradhan, Christos Strydis, Ioannis Sourdis, 2013 .

A multiprocessor network suitable for single-chip VLSI implementation

Dhiraj K. Pradhan, M. R. Samatham, Maheswara R. Samatham, 1984, ISCA '84.

Completely Self-Checking Checkers in PLAs

Dhiraj K. Pradhan, Kyushik Son, 1981, ITC.

A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

The de Bruijn multiprocessor network: a versatile sorting network

Dhiraj K. Pradhan, M. R. Samatham, 1985, ISCA 1985.

An efficient technique for synthesis and optimization of polynomials in GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2006, ICCAD.

20th IEEE International System On Chip Conference (SOCC’ 2007)

Dhiraj K. Pradhan, Argyrides Costas, 2007 .

ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management

Dhiraj K. Pradhan, Saraju P. Mohanty, D. Pradhan, 2010, JETC.

Application of Galois Fields to Logic Synthesis

Dhiraj K. Pradhan, 2008, 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems.

Safe System Level Diagnosis

Dhiraj K. Pradhan, Nitin H. Vaidya, 1994, IEEE Trans. Computers.

Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis

Dhiraj K. Pradhan, Saraju P. Mohanty, Elias Kougianos, 2008, IET Comput. Digit. Tech..

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Elias Kougianos, 2012, Integr..

Selected Articles from the IEEE ISED 2014 Conference

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2015, J. Low Power Electron..

A new algorithm for order statistic and sorting

Dhiraj K. Pradhan, Barun K. Kar, 1993, IEEE Trans. Signal Process..

Subcube Level Time-Sharing in Hypercube Multicomputers

Dhiraj K. Pradhan, Debendra Das Sharma, G. D. Holland, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

A Theory of Galois Switching Functions

Dhiraj K. Pradhan, 1978, IEEE Transactions on Computers.

Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2012, J. Low Power Electron..

Reliability aware yield improvement technique for nanotechnology based circuits

Dhiraj K. Pradhan, Luigi Carro, Costas Argyrides, 2009, SBCCI.

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Garima Thakral, 2010, 2010 23rd International Conference on VLSI Design.

Improved Yield in Nanotechnology Circuits Using Non-square Meshes

Dhiraj K. Pradhan, Costas Argyrides, Nikolaos Mavrogiannakis, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

A hybrid reliability assessment method and its support of sequential logic modelling

Dhiraj K. Pradhan, Samuel Nascimento Pagliarini, Lirida A. B. Naviner, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

Two economical directory schemes for large-scale cache coherent multiprocessors

Dhiraj K. Pradhan, Dominique Thiébaut, Yeong-Chang Maa, 1991, CARN.

Buffer assignment for data driven architectures

Dhiraj K. Pradhan, Savita Banerjee, Mitrajit Chatterjee, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

BCH code based multiple bit error correction in finite field multiplier circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 12th International Symposium on Quality Electronic Design.

Single-Ended SRAM Bitcell Design

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2013 .

Based Checkpoint andd Rollback Recovery

Dhiraj K. Pradhan, N. S. Bowen, D. Pradhan, 1993 .

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP

Dhiraj K. Pradhan, Saraju P. Mohanty, Garima Thakral, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Reliable network-on-chip based on generalized de Bruijn graph

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets

Dhiraj K. Pradhan, Kolar L. Kodandapani, 1980, IEEE Transactions on Computers.

Sequential redundancy identification using recursive learning

Dhiraj K. Pradhan, Wanlin Cao, 1996, Proceedings of International Conference on Computer Aided Design.

Synthesis Techniques and Analysis Tools for On-Chip Fault-Tolerance

Dhiraj K. Pradhan, 1992 .

Yield improvement and power aware low cost memory chips

Dhiraj K. Pradhan, Costas Argyrides, Stephania Loizidou Himona, 2008, WREFT '08.

Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation

Dhiraj K. Pradhan, Debendra Das Sharma, 1995, IEEE Trans. Parallel Distributed Syst..

Fault Tolerant Nanocomputing

Dhiraj K. Pradhan, Saraju P. Mohanty, Bharat Joshi, 2010 .

A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Dhiraj K. Pradhan, Narayanan Vijaykrishnan, Jawar Singh, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Modeling Live and Dead Lines in Cache Memory Systems

Dhiraj K. Pradhan, Dominique Thiébaut, Abraham Mendelson, 1993, IEEE Trans. Computers.

The Effect of Program Behavior on Fault Observability

Dhiraj K. Pradhan, Nicholas S. Bowen, 1996, IEEE Trans. Computers.

Fault tolerant bit parallel finite field multipliers using LDPC codes

Dhiraj K. Pradhan, Jimson Mathew, Jawar Singh, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A Routing-Aware ILS Design Technique

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms

Dhiraj K. Pradhan, Argyrides Costas, Carro Luigi, 2009 .

Design for testability of asynchronous sequential circuits

Dhiraj K. Pradhan, Jayashree Saxena, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms

Dhiraj K. Pradhan, Luigi Carro, Costas Argyrides, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

Dhiraj K. Pradhan, Abusaleh M. Jabir, 2007, IEEE Transactions on Computers.

On the synthesis of attack tolerant cryptographic hardware

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

STEP: a unified design methodology for secure test and IP core protection

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2012, GLSVLSI '12.

Asynchronous State Assignments with Unateness Properties and Fault-Secure Design

Dhiraj K. Pradhan, D. Pradhan, 1978, IEEE Transactions on Computers.

Write scheme for multiple Complementary Resistive Switch (CRS) cells

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2014, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Single element correction in sorting algorithms with minimum delay overhead

Dhiraj K. Pradhan, Luigi Carro, Costas A. Argyrides, 2009, 2009 10th Latin American Test Workshop.

The Hyper-deBruijn Networks: Scalable Versatile Architecture

Dhiraj K. Pradhan, Elango Ganesan, D. Pradhan, 1993, IEEE Trans. Parallel Distributed Syst..

Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model

Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky, 1991, 1991, Proceedings. International Test Conference.

Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci

Dhiraj K. Pradhan, Wolfgang Kunz, D. Pradhan, 1992, Proceedings International Test Conference 1992.

Increasing memory yield in future technologies through innovative design

Dhiraj K. Pradhan, Luigi Carro, Ahmad A. Al-Yamani, 2009, 2009 10th International Symposium on Quality Electronic Design.

Design and Analysis of a Gracefully Degrading Interleaved Memory System

Dhiraj K. Pradhan, Kewal K. Saluja, Gurindar S. Sohi, 1990, IEEE Trans. Computers.

An Efficient De Bruijn Graph Based Fault Tolerant Sensor Networks Design

Dhiraj K. Pradhan, Jimson Mathew, Anas Abu Taleb, 2010, 2010 Fourth International Conference on Sensor Technologies and Applications.

Robust SRAM Designs and Analysis

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2012 .

A fast and effective DFT for test and diagnosis of power switches in SoCs

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fault-tolerant computing: theory and techniques; vol. 1

Dhiraj K. Pradhan, D. Pradhan, 1986 .

A Defect Tolerance Scheme for Nanotechnology Circuits

Dhiraj K. Pradhan, Ahmad A. Al-Yamani, S. Ramsundar, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

A novel approach for subcube allocation in hypercube multiprocessors

Dhiraj K. Pradhan, Debendra Das Sharma, D. Pradhan, 1992, [1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing.

A new class of bit- and byte-error control codes

Dhiraj K. Pradhan, Nitin H. Vaidya, 1992, IEEE Trans. Inf. Theory.

Fault diagnosis in multi layered De Bruijn based architectures for sensor networks

Dhiraj K. Pradhan, Jimson Mathew, Anas Abu Taleb, 2010, 2010 8th IEEE International Conference on Pervasive Computing and Communications Workshops (PERCOM Workshops).

Using memristor state change behavior to identify faults in photovoltaic arrays

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

Dhiraj K. Pradhan, Wolfgang Kunz, D. Pradhan, 1994, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography

Dhiraj K. Pradhan, Dmitri Maslov, Jimson Mathew, 2007, TQC.

Reuse-based test access and integrated test scheduling for network-on-chip

Dhiraj K. Pradhan, Chunsheng Liu, Zach Link, 2006, Proceedings of the Design Automation & Test in Europe Conference.

LOT: Logic Optimization with Testability. New transformations for logic synthesis

Dhiraj K. Pradhan, Wolfgang Kunz, Mitrajit Chatterjee, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Non-square Meshes for Improved Yield in Nanotechnology Circuits

Dhiraj K. Pradhan, S. Ramsundar, Argyrides Costas, 2007 .

Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, IET Comput. Digit. Tech..

The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI

Dhiraj K. Pradhan, M. R. Samatham, Maheswara R. Samatham, 1989, IEEE Trans. Computers.

A placement strategy for reducing the effects of multiple faults in digital circuits

Dhiraj K. Pradhan, Samuel Nascimento Pagliarini, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

A novel memristor based physically unclonable function

Dhiraj K. Pradhan, Jimson Mathew, Durga Prasad Sahoo, 2015, Integr..

A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms

Dhiraj K. Pradhan, Nicholas S. Bowen, 1995, IEEE Trans. Computers.

A Hamming distance based test pattern generator with improved fault coverage

Dhiraj K. Pradhan, Dimitrios Kagaris, Rohit Gambhir, 2005, 11th IEEE International On-Line Testing Symposium.

A BIST Pattern Generator Design for Near-Perfect Fault Coverage

Dhiraj K. Pradhan, Mitrajit Chatterjee, 2003, IEEE Trans. Computers.

C-testable bit parallel multipliers over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, TODE.

A Technique to Identify and Substitute Faulty Nodes in Wireless Sensor Networks

Dhiraj K. Pradhan, Anas Abu Taleb, Taskin Kocak, 2009, 2009 Third International Conference on Sensor Technologies and Applications.

16th Euromicro Conference on Digital System Design

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2013 .

Virtual Checkpoints: Architecture and Performance

Dhiraj K. Pradhan, Nicholas S. Bowen, 1992, IEEE Trans. Computers.

Dynamically Restructurable Fault-Tolerant Processor Network Architectures

Dhiraj K. Pradhan, D. Pradhan, 1985, IEEE Transactions on Computers.

Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems ∗

Dhiraj K. Pradhan, Florin Balasa, Hongwei Zhu, 2008 .

5th International Congress on Image and Signal Processing (CISP 2012)

Dhiraj K. Pradhan, Florin Balasa, 2012 .

Fault-Tolerant Design Strategies for High Reliability and Safety

Dhiraj K. Pradhan, Nitin H. Vaidya, 1993, IEEE Trans. Computers.

NBTI and Its Effect on SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2013 .

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2008, 2008 Design, Automation and Test in Europe.

Sequential Network Design Using Extra Inputs for Fault Detection

Dhiraj K. Pradhan, 1983, IEEE Transactions on Computers.

Fault Tolerant Single Error Correction Encoders

Dhiraj K. Pradhan, Pedro Reviriego, Juan Antonio Maestro, 2011, J. Electron. Test..

NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances

Dhiraj K. Pradhan, Sathiamoorthy Subbarayan, S. Subbarayan, 2004, SAT.

Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2016, IEEE Transactions on Nanotechnology.

Optimal Unidirectional Error Detecting/Correcting Codes

Dhiraj K. Pradhan, Bella Bose, D. Pradhan, 1982, IEEE Transactions on Computers.

VERILAT: verification using logic augmentation and transformations

Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee, 2003, The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003..

Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Garima Thakral, 2010, GLSVLSI '10.

Gate-level synthesis for low-power using new transformations

Dhiraj K. Pradhan, Wolfgang Kunz, Mitrajit Chatterjee, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Consensus With Dual Failure Modes

Dhiraj K. Pradhan, Fred J. Meyer, D. Pradhan, 1991, IEEE Trans. Parallel Distributed Syst..

Recovery in distributed mobile environments

Dhiraj K. Pradhan, Pravin Krishna, Nitin H. Vaidya, 1993, Proceedings 1993 IEEE Workshop on Advances in Parallel and Distributed Systems.

EBIST: a novel test generator with built-in fault detection capability

Dhiraj K. Pradhan, Chunsheng Liu, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A fast error correction technique for matrix multiplication algorithms

Dhiraj K. Pradhan, Luigi Carro, Costas Argyrides, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory

Dhiraj K. Pradhan, Argyrides Costas, Hamid R. Zarandi, 2007 .

TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's

Dhiraj K. Pradhan, Najmi T. Jarwala, 1988, IEEE Trans. Computers.

Multinomial based memristor modelling methodology for simulations and analysis

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2015 .

Failure analysis for ultra low power nano-CMOS SRAM under process variations

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2008, 2008 IEEE International SOC Conference.

Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems

Dhiraj K. Pradhan, Dominique Thiébaut, Abraham Mendelson, 1990, ICPP.

Signal transition graph transformations for initializability

Dhiraj K. Pradhan, Srimat T. Chakradhar, Rabindra K. Roy, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

On the design of different concurrent EDC schemes for S-Box and GF(p)

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Case studies in fault-tolerant multiprocessor and distributed systems

Dhiraj K. Pradhan, 1996 .

A virtual memory translation mechanism to support checkpoint and rollback recovery

Dhiraj K. Pradhan, Nicholas S. Bowen, 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).

Gate-level synthesis for low-power using new transformations

Dhiraj K. Pradhan, Wolfgang Kunz, Mitrajit Chatterjee, 1996, ISLPED.

A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression

Dhiraj K. Pradhan, Sandeep K. Gupta, D. Pradhan, 1991, IEEE Trans. Computers.

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh, 2007, IEEE Transactions on Computers.

A soft error robust and power aware memory design

Dhiraj K. Pradhan, Luigi Carro, Costas Argyrides, 2007, SBCCI '07.

A Fault-Tolerant Communication Architecture for Distributed Systems

Dhiraj K. Pradhan, Sudhakar M. Reddy, S. Reddy, 1982, IEEE Transactions on Computers.

Fault-tolerant parallel computing systems: communication structures in fault-tolerant distributed systems

Dhiraj K. Pradhan, F. J. Meyer, 1992 .

A novel fault diagnosis technique in wireless sensor networks

Dhiraj K. Pradhan, Jimson Mathew, Anas Abu Taleb, 2010 .

Highly Reliable Power Aware Memory Design

Dhiraj K. Pradhan, Costas Argyrides, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Software fault tolerance in parallel computing systems: new roll-forward checkpointing schemes for modular redundant systems

Dhiraj K. Pradhan, Nitin H. Vaidya, N. Vaidya, 1992 .

Complementary resistive switch based stateful logic operations using material implication

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2013, Comput. Electr. Eng..

High level synthesis of data driven ASICs

Dhiraj K. Pradhan, Israel Koren, B. Patel, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Test scheduling for network-on-chip with BIST and precedence constraints

Dhiraj K. Pradhan, Hamid Sharif, Érika F. Cota, 2004, 2004 International Conferce on Test.

Zero aliasing compression

Dhiraj K. Pradhan, Sudhakar M. Reddy, Sandeep K. Gupta, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Optimal broadcasting in binary de Bruijn networks and hyper-deBruijn networks

Dhiraj K. Pradhan, Elango Ganesan, 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

MODD: a new decision diagram and representation for multiple output binary functions

Dhiraj K. Pradhan, Abusaleh M. Jabir, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Techniques to Construct

Dhiraj K. Pradhan, Sudhakar M. Reddy, 1976, IEEE Transactions on Computers.

Software Modification Aided Transient Error Tolerance for Embedded Systems

Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis, 2013, 2013 Euromicro Conference on Digital System Design.

Communication structures in fault-tolerant distributed systems

Dhiraj K. Pradhan, Fred J. Meyer, D. Pradhan, 1993, Networks.

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance

Dhiraj K. Pradhan, Zhen Li, Jimson Mathew, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A method to derive compact test sets for path delay faults in combinational circuits

Dhiraj K. Pradhan, Jayashree Saxena, D. Pradhan, 1993, Proceedings of IEEE International Test Conference - (ITC).

A Novel Frame ork for Logic cation in a Synthesis Environment

Dhiraj K. Pradhan, Wolfgang Kunz, S. M. Reddy, 1996 .

GLFSR-a new test pattern generator for built-in-self-test

Dhiraj K. Pradhan, Mitrajit Chatterjee, D. Pradhan, 1994, Proceedings., International Test Conference.

Modeling Defect Spatial Distribution

Dhiraj K. Pradhan, Fred J. Meyer, D. Pradhan, 1989, IEEE Trans. Computers.

Single-Event Transient Analysis in High Speed Circuits

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 International Symposium on Electronic System Design.

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, J. Low Power Electron..

Design Automation and Test in Europe (DATE)

Dhiraj K. Pradhan, Jimson Mathew, Luo Sun, 2014 .

Logic insertion to speed-up logic verification: a recent development

Dhiraj K. Pradhan, 2001, Proceedings Seventh International On-Line Testing Workshop.

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework

Dhiraj K. Pradhan, Saraju P. Mohanty, Bashir M. Al-Hashimi, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Degradable Byzantine agreement

Dhiraj K. Pradhan, Nitin H. Vaidya, N. Vaidya, 1995 .

BDG-torus union graph-an efficient algorithmically specialized parallel interconnect

Neeraj Suri, Dhiraj K. Pradhan, Avi Mendelson, 1991, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing.

Practical Design Verification

Dhiraj K. Pradhan, Ian G. Harris, 2009 .

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, IEEE Transactions on Computers.

Reed-Muller Like Canonic Forms for Multivalued Functions

Dhiraj K. Pradhan, Arvind M. Patel, D. Pradhan, 1975, IEEE Transactions on Computers.

Low Power and Robust Binary Tree SRAM Design for Embedded Systems

Dhiraj K. Pradhan, Jimson Mathew, Luo Sun, 2013, 2013 International Symposium on Electronic System Design.

An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a

Dhiraj K. Pradhan, Dmitri Maslov, Jimson Mathew, 2009, Quantum Inf. Comput..

Layout-aware Illinois Scan design for high fault coverage coverage

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Job Scheduling in Mesh Multicomputers

Dhiraj K. Pradhan, Debendra Das Sharma, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

Fault Injection: A Method for Validating Computer-System Dependability

Dhiraj K. Pradhan, Jeffrey A. Clark, D. Pradhan, 1995, Computer.

Improving performance of TCP over wireless networks

Dhiraj K. Pradhan, Nitin H. Vaidya, B. S. Bakshi, 1997, Proceedings of 17th International Conference on Distributed Computing Systems.

A design for testability scheme to reduce test application time in full scan

Dhiraj K. Pradhan, Jayashree Saxena, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction

Dhiraj K. Pradhan, Fabian Vargas, Costas Argyrides, 2011, IEEE Transactions on Reliability.

An efficient coordinated checkpointing scheme for multicomputers

Dhiraj K. Pradhan, Debendra Das Sharma, 1994, Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems.

Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture

Dhiraj K. Pradhan, Nitin H. Vaidya, N. Vaidya, 1994, IEEE Trans. Computers.

Fault-Tolerance in Distributed and Multiprocessor Real-Time Systems

Dhiraj K. Pradhan, 1993 .

A single ended 6T SRAM cell design for ultra-low-voltage applications

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2008, IEICE Electron. Express.

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2011, 2011 24th Internatioal Conference on VLSI Design.

A Galois Field Based Logic Synthesis Approach with Testability

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, 21st International Conference on VLSI Design (VLSID 2008).

11th IEEE International Symposium on Quality Electronic Design (ISQED)

Dhiraj K. Pradhan, G. Thakral, P. MohantyS., 2010 .

Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay

Dhiraj K. Pradhan, Israel Koren, Zahava Koren, 1988 .

DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM

Dhiraj K. Pradhan, Saraju P. Mohanty, Elias Kougianos, 2010, J. Low Power Electron..

Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties)

Dhiraj K. Pradhan, D. Pradhan, 1989, Reliability Of Computer And Communication Networks.

Error-control coding in computers

Dhiraj K. Pradhan, Eiji Fujiwara, 1990, Computer.

Functional learning: a new approach to learning in digital circuits

Dhiraj K. Pradhan, Rajarshi Mukherjee, Jawahar Jain, 1994, Proceedings of IEEE VLSI Test Symposium.

Matching in memristor based auto-associative memory with application to pattern recognition

Dhiraj K. Pradhan, Jimson Mathew, Yuanfan Yang, 2014, 2014 12th International Conference on Signal Processing (ICSP).

A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications

Dhiraj K. Pradhan, Jimson Mathew, Babita R. Jose, 2007, 2007 IEEE International SOC Conference.

Error-Correcting Codes and Self-Checking Circuits

Dhiraj K. Pradhan, Jack J. Stiffler, D. Pradhan, 1980, Computer.

A Cluster-based Approach for Routing in Ad-Hoc Networks

Dhiraj K. Pradhan, Nitin H. Vaidya, Mainak Chatterjee, 1995, Symposium on Mobile and Location-Independent Computing.

Selected Articles from the IEEE ISED 2016 Conference

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2017, J. Low Power Electron..

Area Reliability Trade-Off in Improved Reed Muller Coding

Dhiraj K. Pradhan, Costas Argyrides, Stephania Loizidou, 2008, SAMOS.

Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa

Dhiraj K. Pradhan, Sandeep K. Gupta, 1996, IEEE Trans. Computers.

LPRAM: a novel low-power high-performance RAM design with testability and scalability

Dhiraj K. Pradhan, Subhasis Bhattacharjee, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thermal-aware testing of network-on-chip using multiple-frequency clocking

Dhiraj K. Pradhan, Chunsheng Liu, Vikram Iyengar, 2006, 24th IEEE VLSI Test Symposium.

Improved decoding algorithm for high reliable reed muller coding

Dhiraj K. Pradhan, Costas Argyrides, 2007, 2007 IEEE International SOC Conference.

Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

Dhiraj K. Pradhan, Jimson Mathew, Mohammad Reza Kakoee, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Job Scheduling in Mesh Multicomputers

Dhiraj K. Pradhan, Debendra Das Sharma, 1998, IEEE Trans. Parallel Distributed Syst..

Test Generation in Systolic Architecture for Multiplication Over $GF(2 ^{m})$

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reversible Logic: An Introduction

Dhiraj K. Pradhan, Trailokya Nath Sasamal, Ashutosh Kumar Singh, 2019, Lecture Notes in Electrical Engineering.

Single Error Correcting Finite Field Multipliers Over GF(2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2008, 21st International Conference on VLSI Design (VLSID 2008).

IEEE International Conference on VLSI Design (VLSID)

Dhiraj K. Pradhan, Saraju P. Mohanty, Garima Thakral, 2010 .

REACT: An Integrated Tool for the Design of Dependable Computing Systems

Dhiraj K. Pradhan, Jeffrey A. Clark, D. Pradhan, 1994 .

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

Dhiraj K. Pradhan, Ahmad A. Al-Yamani, S. Ramsundar, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Fault-Tolerant Computing

Dhiraj K. Pradhan, Bharat Joshi, Jack J. Stiffler, 2008, Wiley Encyclopedia of Computer Science and Engineering.

DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs

Dhiraj K. Pradhan, Babak Falsafi, Christos-Savvas Bouganis, 2014, ARC.

High defect tolerant low cost memory chips

Dhiraj K. Pradhan, Ahmad A. Al-Yamani, Costas Argyrides, 2007, 2007 IEEE International SOC Conference.

VERILAT: Verification by Logic Augmentation and Transformation

Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee, 2000 .

Design Techniques for Synthesis of Fault-Tolerant Asynchronous Networks.

Dhiraj K. Pradhan, Sudhakar M. Reddy, 1972 .

Introduction to Energy-Efficient Fault-Tolerant Systems

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2014 .

Logic Verification in a Synthesis Environment

Dhiraj K. Pradhan, Wolfgang Kunz, S. M. Reddy, 2001 .

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Dagstuhl Seminar Proceedings on Fault-Tolerant Distributed Algorithms on VLSI Chips

Dhiraj K. Pradhan, Argyrides Costas, 2009 .

Fault-Tolerant Multiprocessor Link and Bus Network Architectures

Dhiraj K. Pradhan, 1985, IEEE Transactions on Computers.

Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation

Dhiraj K. Pradhan, Jimson Mathew, Urbi Chatterjee, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Investigating the impact of NBTI on different power saving cache strategies

Dhiraj K. Pradhan, Narayanan Vijaykrishnan, Jawar Singh, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Efficient Location Management in Mobile Wireless Networks

Dhiraj K. Pradhan, Nitin H. Vaidya, Pravin Krishna, 1996 .

Wormhole routing in de Bruijn networks and hyper-de Bruijn networks

Dhiraj K. Pradhan, Elango Ganesan, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Program fault tolerance based on memory access behavior

Dhiraj K. Pradhan, Nicholas S. Bowen, 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

Accelerated dynamic learning for test pattern generation in combinational circuits

Dhiraj K. Pradhan, Wolfgang Kunz, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Comparative study of CA with phase shifters and GLFSRs

Dhiraj K. Pradhan, Dimitrios Kagaris, S. Chidambaram, 2005, IEEE International Conference on Test, 2005..

Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs

Dhiraj K. Pradhan, Dimitrios Kagaris, Jayawant Kakade, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A nano-CMOS process variation induced read failure tolerant SRAM cell

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Location management in distributed mobile environments

Dhiraj K. Pradhan, Nitin H. Vaidya, P. Krishna, 1994, Proceedings of 3rd International Conference on Parallel and Distributed Information Systems.

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Costas Argyrides, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Modified tree structure for location management in mobile environments

Dhiraj K. Pradhan, Jennifer L. Welch, Shlomi Dolev, 1995, Comput. Commun..

Improving reliability for bit parallel finite field multipliers using Decimal Hamming

Dhiraj K. Pradhan, Costas Argyrides, Nikolaos Mavrogiannakis, 2010, 2010 East-West Design & Test Symposium (EWDTS).

Sequential redundancy identification using recursive learning

Dhiraj K. Pradhan, Wanlin Cao, 1996, ICCAD 1996.

Fault-tolerant multiprocessor and distributed systems: principles

Dhiraj K. Pradhan, Prith Banerjee, 1996 .

Application specific VLSI architectures based on De Bruijn graphs

Dhiraj K. Pradhan, 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

Store Address Generator with On-Line Fault-Detection Capability

Dhiraj K. Pradhan, Arvind M. Patel, M. Y. Hsiao, 1977, IEEE Transactions on Computers.

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment

Dhiraj K. Pradhan, Wolfgang Kunz, Subodh M. Reddy, 1995, 32nd Design Automation Conference.

Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors

Dhiraj K. Pradhan, Debendra Das Sharma, D. Pradhan, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Logic transformation and coding theory-based frameworks for Boolean satisfiability

Dhiraj K. Pradhan, D. Pradhan, 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

Recoverable mobile environment: design and trade-off analysis

Dhiraj K. Pradhan, Nitin H. Vaidya, P. Krishna, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Argyrides Costas, 2007 .

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2015, IEEE Transactions on Reliability.

International Conference on Eco-friendly Computing and Communication Systems (ICECCS )

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2012, ICECCS 2012.

C-testable S-box implementation for secure advanced encryption standard

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2009, 2009 15th IEEE International On-Line Testing Symposium.

LOT: logic optimization with testability—new transformations using recursive learning

Dhiraj K. Pradhan, Wolfgang Kunz, Mitrajit Chatterjee, 1995, ICCAD.

Test scheduling for network-on-chip with BIST and precedence constraints

Dhiraj K. Pradhan, Hamid Sharif, Chunsheng Liu, 2004 .

A New Algorithm For Order Statistic

Dhiraj K. Pradhan, B. K. Kar, 1992, Workshop on VLSI Signal Processing.

Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection

Dhiraj K. Pradhan, Jimson Mathew, Abusaleh M. Jabir, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis

Dhiraj K. Pradhan, Jimson Mathew, Mohamad Imran Bin Bandan, 2013, 2013 International Symposium on Electronic System Design.

Roll-Forward Checkpointing Schemes

Dhiraj K. Pradhan, Nitin H. Vaidya, Debendra Das Sharma, 1993, Hardware and Software Architectures for Fault Tolerance.

A Novel Memristor-Based Hardware Security Primitive

Dhiraj K. Pradhan, Jimson Mathew, Durga Prasad Sahoo, 2015, ACM Trans. Embed. Comput. Syst..

Forwarding Pointers for Efficient Location Management in Distributed Mobile Environments

Dhiraj K. Pradhan, Nitin H. Vaidya, Pravin Krishna, 1994 .

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2012, VDAT.

Fault Tolerant High Performance Galois Field Arithmetic Processor

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2012, ICECCS 2012.

Multiple Upsets Tolerance in SRAM Memory

Dhiraj K. Pradhan, Costas Argyrides, Hamid R. Zarandi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

Dhiraj K. Pradhan, Jimson Mathew, Marco Ottavi, 2016, IEEE Transactions on Nanotechnology.

Sharing patterns and the single cachable coherence scheme for shared memory systems

Dhiraj K. Pradhan, Abraham Mendelson, 1990 .

Matrix Codes for Reliable and Cost Efficient Memory Chips

Dhiraj K. Pradhan, Taskin Koçak, Costas Argyrides, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications

Dhiraj K. Pradhan, D. Pradhan, 1980, IEEE Transactions on Computers.

Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System

Dhiraj K. Pradhan, Jimson Mathew, Mohamad Imran Bin Bandan, 2014, J. Low Power Electron..

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs

Dhiraj K. Pradhan, Jimson Mathew, Seyed Ghassem Miremadi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

The de Bruijn multiprocessor network: a versatile sorting network

Dhiraj K. Pradhan, M. R. Samatham, Maheswara R. Samatham, 1985, ISCA '85.

A METHOD FOR VM-IDATING COMPUTER-SYSTEM DEPENDABILITY

Dhiraj K. Pradhan, Jeffrey A. Clark, 1995 .

LOT: Logic optimization with testability - new transformations using recursive learning

Dhiraj K. Pradhan, Wolfgang Kunz, Mitrajit Chatterjee, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Multinomial Memristor Model for Simulations and Analysis

Dhiraj K. Pradhan, Jimson Mathew, Li Gang, 2013, 2013 International Symposium on Electronic System Design.

LPRAM: a low power DRAM with testability

Dhiraj K. Pradhan, Subhasis Bhattacharjee, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A novel scheme to reduce test application time in circuits with full scan

Dhiraj K. Pradhan, Jayashree Saxena, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design of Two-Level Fault-Tolerant Networks

Dhiraj K. Pradhan, Sudhakar M. Reddy, 1974, IEEE Transactions on Computers.

Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs

Dhiraj K. Pradhan, Seyed Ghassem Miremadi, Argyrides Costas, 2007 .

Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

Recovery in Mobile Wireless Environment: Design and Trade-off Analysis

Dhiraj K. Pradhan, Nitin H. Vaidya, P. V. Murali Krishna, 1996 .

Single ended 6T SRAM with isolated read-port for low-power embedded systems

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Clustered De Bruijn Based Multi Layered Architectures for Sensor Networks

Dhiraj K. Pradhan, Jimson Mathew, Anas Abu Taleb, 2010 .

On a Class of Fault-Tolerant Multiprocessor Network Architectures

Dhiraj K. Pradhan, 1982, ICDCS.

2-Port SRAM Bitcell Design

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2013 .

Buffer Assignment Algorithms on Data Driven ASICs

Dhiraj K. Pradhan, Savita Banerjee, Mitrajit Chatterjee, 2000, IEEE Trans. Computers.

22nd annual symposium on Integrated circuits and system design SBCCI ‘09

Dhiraj K. Pradhan, Argyrides Costas, Carro Luigi, 2009 .

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Processor- and memory-based checkpoint and rollback recovery

Dhiraj K. Pradhan, Nicholas S. Bowen, 1993, Computer.

Design Metrics of SRAM Bitcell

Dhiraj K. Pradhan, Saraju P. Mohanty, Jawar Singh, 2013 .

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

Dhiraj K. Pradhan, Jimson Mathew, Rishad A. Shafik, 2014, IEEE Embedded Systems Letters.

Instantaneous Mean-Time-To-Failure (MTTF)estimation for checkpoint interval computation at run time

Dhiraj K. Pradhan, Suriati Khartini Jali, Subhasis Bhattacharjee, 2019 .

Tutorial: Recent Advances in Verification, Equivalence Checking & SAT-Solvers Speakers

Dhiraj K. Pradhan, Mauricio Varea, Magdy S. Abadir, 2005 .

Integrated Circuit Manufacturability

Dhiraj K. Pradhan, Jos¿ Pineda de Gyvez, D. Pradhan, 1998 .

The DeSyRe Project: On-Demand System Reliability

Dhiraj K. Pradhan, Babak Falsafi, Christos-Savvas Bouganis, 2012, 2012 15th Euromicro Conference on Digital System Design.

Providing seamless communication in mobile wireless networks

Dhiraj K. Pradhan, Nitin H. Vaidya, P. Krishna, 1996, Proceedings of LCN - 21st Annual Conference on Local Computer Networks.

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

Dhiraj K. Pradhan, Jimson Mathew, Hafizur Rahaman, 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

Low Power and Robust Binary Tree SRAM Design for Embedded Systems: 2013 International Symposium on Electronic System Design

Dhiraj K. Pradhan, Jimson Mathew, 2013 .

Fault-Tolerant Computing

Dhiraj K. Pradhan, 1980, Computer.

A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines

Dhiraj K. Pradhan, Kolar L. Kodandapani, 1980, IEEE Transactions on Computers.

Lecture note in Computer Science

Dhiraj K. Pradhan, Hafizur Rahaman, Jimson Mathew, 2012 .

Galois Switching Theory: A Uniform Framework for Multi-Level Verification

Dhiraj K. Pradhan, Abusaleh M. Jabir, A. D. Singh, 2005 .

SHIFT REGISTERS DESIGNED FOR ON-LINE FAULT DETECTION

Dhiraj K. Pradhan, M. Y. Hsiao, A. M. Patel, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

Recoverable Mobile Environments : Design andTrade-o Analysis

Dhiraj K. Pradhan, H. Nitin, P. Krishna, 1996 .

Great Lakes Symposium on VLSI (GLSVLSI)

Dhiraj K. Pradhan, Jimson Mathew, Saraju P. Mohanty, 2012 .