Jason Cong

Jason Cong, Glenn Reinman, Zhenman Fang, 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Enhanced robustness in multilevel mixed-size placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005 .

Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management

Jason Cong, Yun Liang, Xuechao Wei, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Interconnect oriented microarchitectures and resource binding in behavioral synthesis

Jason Cong, Yiping Fan, 2006 .

From milliwatts to megawatts : System level power challenge

Jason Cong, John Shen, Ruchir Puri, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Parallel logic level simulation of VLSI circuits

Jason Cong, Zheng Li, Yuan Chen, 1994, Proceedings of Winter Simulation Conference.

The DIMM tree architecture: A high bandwidth and scalable memory system

Jason Cong, Glenn Reinman, Kanit Therdsteerasukdi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Energy efficient multiprocessor task scheduling under input-dependent variation

Jason Cong, Karthik Gururaj, J. Cong, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

On the k-layer planar subset and topological via minimization problems

Jason Cong, C. L. Liu, J. Cong, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung, 1997, ISPD '97.

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Jason Cong, Peng Li, Peng Zhang, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thermal-driven multilevel routing for 3-D ICs

Jason Cong, Yan Zhang, J. Cong, 2005, Asia and South Pacific Design Automation Conference.

Interconnect Performance Estimation Models For Synthesis And Design Planning

Jason Cong, Zhigang Pan, 1998 .

Optimal FPGA mapping and retiming with efficient initial state computation

Jason Cong, Chang Wu, 1998, DAC.

Optimality Study of Existing Quantum Computing Layout Synthesis Tools pdf

Jason Cong, Bochen Tan, J. Cong, 2020, IEEE Transactions on Computers.

Wire width planning for interconnect performance optimization

Jason Cong, David Z. Pan, J. Cong, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Incremental physical design

Jason Cong, Majid Sarrafzadeh, J. Cong, 2000, ISPD '00.

Optimality, scalability and stability study of partitioning and placement algorithms

Jason Cong, Min Xie, Michail Romesis, 2003, ISPD '03.

Via Minimization by Layout Modification

Jason Cong, Martin D. F. Wong, Khe-Sing The, 1989, 26th ACM/IEEE Design Automation Conference.

Platform-based synthesis for field-programmable SOCs

Jason Cong, 2005 .

Accelerator-rich architectures — from single-chip to datacenters

Jason Cong, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Automatic Interior I/O Elimination in Systolic Array Architecture

Jason Cong, Jie Wang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections

Jason Cong, Peng Zhang, Yi Zou, 2012, J. Electr. Comput. Eng..

Fault Covers in Heterogeneous and General Arrays

Jason Cong, Ran Libeskind-Hadas, Nany Hasan, 1992 .

Multi-layer general area gridless detailed routing

Jason Cong, Jie Fang, 2001 .

Multi-way partitioning using bi-partition heuristics

Jason Cong, Majid Sarrafzadeh, Maogang Wang, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Accelerator-Rich Architectures — Computing Beyond Processors

Jason Cong, 2015 .

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators

Jason Cong, Chen Zhang, Yijin Guan, 2017, APPT.

Simultaneous Buffer and Wire Sizing for Performaince and Power

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996 .

Layout optimization and planning in deep sub-micron vlsi designs

Jason Cong, Chin-Chih Chang, 2002 .

Synthesis for high-density and high-performance fpgas

Jason Cong, Songjie Xu, 2000 .

Simultaneous placement with clustering and duplication

Jason Cong, Gang Chen, 2006, ACM Trans. Design Autom. Electr. Syst..

Interconnect layout optimization under higher order RLC model forMCM designs

Jason Cong, Cheng-Kok Koh, Patrick H. Madden, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Jason Cong, Yiping Fan, Junjuan Xu, 2009, TODE.

FPGA acceleration by asynchronous parallelization for simultaneous image reconstruction and segmentation based on the Mumford-Shah regularization

Jason Cong, Peng Li, Ming Jiang, 2015, SPIE Optical Engineering + Applications.

EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation

Jason Cong, Ming Yan, Alex A. T. Bui, 2011, ISVC.

Thermal-Aware 3D Floorplan

Jason Cong, Yuchun Ma, J. Cong, 2010 .

Modern Circuit Placement, Best Practices and Results

Jason Cong, Gi-Joon Nam, 2007 .

Optimality Study of Logic Synthesis for LUT-Based FPGAs

Jason Cong, Kirill Minkovich, J. Cong, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simultaneous FU and Register Binding Based on Network Flow Method

Jason Cong, Junjuan Xu, J. Cong, 2008, 2008 Design, Automation and Test in Europe.

2019 DAC Roundtable

Jason Cong, Giovanni De Micheli, Antun Domic, 2020, IEEE Des. Test.

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization

Jason Cong, Zhiru Zhang, Bin Liu, 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

Performance-driven global routing for cell based ICs

Jason Cong, Chak-Kuen Wong, Majid Sarrafzadeh, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Better-Than-Worst-Case Design: Progress and Opportunities

Jason Cong, Rakesh Kumar, Sen Li, 2014, Journal of Computer Science and Technology.

A New Approach to Three Layer Channel Routing

Jason Cong, 1987 .

Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework

Jason Cong, Zhenman Fang, Peipei Zhou, 2018, 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

VIA design rule consideration in multi-layer maze routing algorithms

Jason Cong, Jie Fang, Kei-Yong Khoo, 1999, ISPD '99.

Multilevel Granularity Parallelism Synthesis on FPGAs

Jason Cong, Yun Liang, Deming Chen, 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

Memory partitioning and scheduling co-optimization in behavioral synthesis

Jason Cong, Peng Li, Peng Zhang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Timing closure based on physical hierarchy

Jason Cong, 2002, ISPD '02.

Interconnect sizing and spacing with consideration of couplingcapacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A layout modification approach to via minimization

Jason Cong, Martin D. F. Wong, Khe-Sing The, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

Jason Cong, Sung Kyu Lim, Toshiyuki Shibuya, 1997, ICCAD 1997.

Simultaneous logic decomposition with technology mapping in FPGA designs

Jason Cong, Gang Chen, 2001, FPGA '01.

Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system

Jason Cong, Glenn Reinman, Kanit Therdsteerasukdi, 2012, TACO.

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

Jason Cong, Yuzheng Ding, 1993, ICCAD.

An integrated and automated memory optimization flow for FPGA behavioral synthesis

Jason Cong, Peng Zhang, Yuxin Wang, 2012, 17th Asia and South Pacific Design Automation Conference.

Designing scratchpad memory architecture with emerging STT-RAM memory technologies

Jason Cong, Yuan Xie, Guangyu Sun, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis

Jason Cong, Jie Liu, 2019, FPGA.

Optimizing memory hierarchy allocation with loop transformations for high-level synthesis

Jason Cong, Peng Zhang, Yi Zou, 2012, DAC Design Automation Conference 2012.

A-QED Verification of Hardware Accelerators

Jason Cong, Zhiru Zhang, Peng Wei, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Theory and algorithm for generalized memory partitioning in high-level synthesis

Jason Cong, Peng Li, Yuxin Wang, 2014, FPGA.

Bounded-skew clock and Steiner routing under Elmore delay

Jason Cong, Cheng-Kok Koh, Andrew B. Kahng, 1995, ICCAD.

Theory and Algorithm for SPFD-Based Global Rewiring

Jason Cong, 2001 .

Optimal module and voltage assignment for low-power

Jason Cong, Deming Chen, Junjuan Xu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

The new line in IC design

Jason Cong, Tsu-Chang Lee, 1997 .

Analyzing and Modeling In-Storage Computing Workloads On EISC — An FPGA-Based System-Level Emulation Platform

Jason Cong, Tong He, Zhenyuan Ruan, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FPGA Technology Mapping

Jason Cong, Yuzheng Ding, 2016, Encyclopedia of Algorithms.

A provably good multilayer topological planar routing algorithm in IC layout designs

Jason Cong, Moazzem Hossain, Naveed A. Sherwani, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An interconnect-centric design flow for nanometer technologies

Jason Cong, J. Cong, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs

Jason Cong, Yuan Xie, Yijin Guan, 2020, IEEE Transactions on Computers.

A new approach to three- or four-layer channel routing

Jason Cong, Martin D. F. Wong, C. L. Liu, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Challenges and Solutions for Nanometer SOC Designs

Jason Cong, 2004 .

Advances and Challenges in 3D Physical Design (IPSJ Transactions on System LSI Design Methodology Vol.3)

Jason Cong, Guojie Luo, 2010 .

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs

Jason Cong, Jie Wang, Yun Liang, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Optimization of interconnects between accelerators and shared memories in dark silicon

Jason Cong, Bingjun Xiao, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Jason Cong, Deming Chen, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Pseudopin assignment with crosstalk noise control

Jason Cong, Chin-Chih Chang, J. Cong, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures pdf

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, ArXiv.

Performance-driven mapping for CPLD architectures

Jason Cong, Milos D. Ercegovac, Deming Chen, 2001, FPGA '01.

CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only)

Jason Cong, Zhenman Fang, Di Wu, 2017, FPGA.

On area/depth trade-off in LUT-based FPGA technology mapping

Jason Cong, Yuzheng Ding, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing

Jason Cong, Lei He, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Tutorial and Survey Paper Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays

Jason Cong, Yuzheng Ding, 1996 .

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Jason Cong, Deming Chen, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Improved SAT-based Boolean matching using implicants for LUT-based FPGAs

Jason Cong, Kirill Minkovich, J. Cong, 2007, FPGA '07.

Multi-level coarse placement for physical hierarchy generation

Jason Cong, Xin Yuan, 2003 .

Bit-level optimization for high-level synthesis and FPGA-based acceleration

Jason Cong, Zhiru Zhang, Sheng Zhou, 2010, FPGA '10.

End-to-End Optimization of Deep Learning Applications

Jason Cong, Jie Wang, Atefeh Sohrabizadeh, 2020, FPGA.

Rapid Cycle-Accurate Simulator for High-Level Synthesis

Jason Cong, Jie Wang, Yuze Chi, 2019, FPGA.

Assuring application-level correctness against soft errors

Jason Cong, Karthik Gururaj, J. Cong, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

HLScope: High-Level Performance Debugging for FPGA Designs

Jason Cong, Young Kyu Choi, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Interconnect design for deep submicron ICs

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs

Jason Cong, Yean-Yow Hwang, J. Cong, 2000, TODE.

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping

Jason Cong, Yean-Yow Hwang, J. Cong, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Atlas: Baidu's key-value storage system for cloud data

Jason Cong, Song Jiang, Guangyu Sun, 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

Throughput-oriented kernel porting onto FPGAs

Jason Cong, Yun Liang, Deming Chen, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Logic synthesis for nanometer ic technologies

Jason Cong, Kirill Minkovich, 2010 .

Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources

Jason Cong, Songjie Xu, 1998, ICCAD.

ACES: Application-specific cycle elimination and splitting for deadlock-free routing on irregular Network-on-Chip

Jason Cong, Glenn Reinman, Chunyue Liu, 2010, Design Automation Conference.

System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project

Jason Cong, Majid Sarrafzadeh, Wenyao Xu, 2014, IEEE Journal of Biomedical and Health Informatics.

CMOST: A system-level FPGA compilation framework

Jason Cong, Peng Zhang, Muhuan Huang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

RF interconnects for communications on-chip

Jason Cong, Mau-Chung Frank Chang, Eran Socher, 2008, ISPD '08.

Efficient system-level mapping from streaming applications to FPGAs (abstract only)

Jason Cong, Peng Zhang, Muhuan Huang, 2013, FPGA '13.

A Novel High-Throughput Acceleration Engine for Read Alignment

Jason Cong, Peng Wei, Jie Lei, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

FPGA-based accelerator for long short-term memory recurrent neural networks

Jason Cong, Guangyu Sun, Yijin Guan, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

FPGA Implementation of EM Algorithm for 3D CT Reconstruction

Jason Cong, Di Wu, Young Kyu Choi, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

HC-Sim: A fast and exact L1 cache simulator with scratchpad memory co-simulation support

Jason Cong, Glenn Reinman, Yu-Ting Chen, 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation

Jason Cong, Yi Zou, 2009, TRETS.

Architecture Evaluation for FPGAs with Embedded Memory Blocks

Jason Cong, Songjie Xu, 1998 .

Behavior and communication co-optimization for systems with sequential communication media

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Architecture support for accelerator-rich CMPs

Jason Cong, Glenn Reinman, Michael Gill, 2012, DAC Design Automation Conference 2012.

Optimality and Stability Study of Timing-Driven Placement Algorithms

Jason Cong, Min Xie, Michail Romesis, 2003, ICCAD.

An interconnect-centric design flow for nanometer technologies

Jason Cong, J. Cong, 2001, Proc. IEEE.

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

Jason Cong, Glenn Reinman, Yuchun Ma, 2008, JETC.

Gradual Relaxation Techniques with Applications to Behavioral Synthesis

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2003, ICCAD 2003.

Evaluating Statistical Power Optimization

Jason Cong, Puneet Gupta, John Lee, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Large-Scale Global Placement

Jason Cong, Joseph R. Shinnerl, J. Cong, 2018, Handbook of Approximation Algorithms and Metaheuristics.

PolySA: Polyhedral-Based Systolic Array Auto-Compilation

Jason Cong, Jie Wang, J. Cong, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An efficient and versatile scheduling algorithm based on SDC formulation

Jason Cong, Zhiru Zhang, J. Cong, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment

Peng Zhang, Jason Cong, Cody Hao Yu, 2019, FPGA.

Combining module selection and replication for throughput-driven streaming programs

Jason Cong, Bin Liu, Muhuan Huang, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Pin assignment with global routing

Jason Cong, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

A scalable micro wireless interconnect structure for CMPs

Jason Cong, Songwu Lu, Lixia Zhang, 2009, MobiCom '09.

An Integer Linear Programming Approach to General Fault Covering Problems

Jason Cong, C. L. Liu, N. Hasan, 1990 .

An implicit connection graph maze routing algorithm for ECO routing

Jason Cong, Jie Fang, Kei-Yong Khoo, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Jason Cong, Andrew B. Kahng, Lei He, 1997, DAC.

FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only)

Jason Cong, Peng Li, Li Shen, 2015, FPGA.

A cache-based bandwidth optimized motion compensation architecture for video decoder

Jason Cong, Wen Gao, Huizhu Jia, 2017, 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Multilevel Circuit Placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2003 .

Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs

Peng Zhang, Jason Cong, Cody Hao Yu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Improving high level synthesis optimization opportunity through polyhedral transformations

Jason Cong, Peng Li, Yun Liang, 2013, FPGA '13.

Jason Cong, Deming Chen, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

3D Physical Design

Jason Cong, Guojie Luo, J. Cong, 2011 .

An enhanced multilevel routing system

Jason Cong, Min Xie, Yan Zhang, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

An improved graph-based FPGA technology mapping algorithm for delay optimization

Jason Cong, Andrew B. Kahng, Kuang-Chien Chen, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Channel Density Minimization by Pin Permutation

Jason Cong, Yang Cai, D. F. Wong, 1994 .

Pattern-based behavior synthesis for FPGA resource reduction

Jason Cong, Wei Jiang, 2008, FPGA '08.

Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion

Jason Cong, J. Cong, 1996 .

A New Approach to Three- or

Jason Cong, C. L. Liu, D. F. Wong, 1988 .

Compilation and architecture support for customized vector instruction extension

Jason Cong, Bin Liu, Glenn Reinman, 2012, 17th Asia and South Pacific Design Automation Conference.

Characterization and acceleration for genomic sequencing and analysis

Jason Cong, 2017, IISWC.

Global clustering-based performance-driven circuit partitioning

Jason Cong, Chang Wu, J. Cong, 2002, ISPD '02.

Automatic memory partitioning and scheduling for throughput and power optimization

Jason Cong, Bin Liu, Wei Jiang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs

Jason Cong, Yu Wang, Sheqin Dong, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Provably good performance-driven global routing

Jason Cong, Chak-Kuen Wong, Majid Sarrafzadeh, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics

Jason Cong, Fei Li, Yan Lin, 2004, FPGA '04.

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Jason Cong, Zhenman Fang, Yuchen Hao, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Fast floorplanning by look-ahead enabled recursive bipartitioning

Joseph R. Shinnerl, Jason Cong, Michail Romesis, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs

Jason Cong, Glenn Reinman, Chunyue Liu, 2012, ISLPED '12.

Large-Scale Circuit Placement: Gap and Promise

Joseph R. Shinnerl, Jason Cong, Min Xie, 2003, ICCAD.

A reuse-aware prefetching scheme for scratchpad memory

Jason Cong, Yi Zou, Hui Huang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators pdf

Jason Cong, Cody Hao Yu, Min Gao, 2020, FPGA.

An analytical placer for mixed-size 3D placement

Jason Cong, Guojie Luo, 2010, ISPD '10.

Nonconvex Optimization and Its Applications

Joseph R. Shinnerl, Jason Cong, Min Xie, 2013 .

Performance driven global routing for standard cell design

Jason Cong, Patrick H. Madden, 1997, ISPD '97.

Simultaneous driver and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Optimal Layout Synthesis for Quantum Computing

Jason Cong, Bochen Tan, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Session details: Session 9C: Advances in placement

Jason Cong, Patrick Groeneveld, 2001, ICCAD 2001.

A thermal-driven floorplanning algorithm for 3D ICs

Jason Cong, Jie Wei, Yan Zhang, 2004, ICCAD 2004.

Partially-dependent functional decomposition with applications in FPGA synthesis and mapping

Jason Cong, Yean-Yow Hwang, 1997, FPGA '97.

FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow

Jason Cong, Ying Chen, Yun Liang, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Pin assignment with global routing for general cell designs

Jason Cong, J. Cong, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

HLScope+,: Fast and accurate performance estimation for FPGA HLS

Peng Zhang, Jason Cong, Peng Li, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only)

Jason Cong, Zhe Chen, Hugh T. Blair, 2018, FPGA.

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates

Xi Chen, Wei Zhang, Jason Cong, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices

Jason Cong, Zhe Chen, Hugh T. Blair, 2020, ISLPED.

Energy-efficient computing using adaptive table lookup based on nonvolatile memories

Jason Cong, Milos D. Ercegovac, Muhuan Huang, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Customizable domain-specific computing

Jason Cong, 2009, FPL.

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs

Jason Cong, Xin Yuan, Hui Huang, 2005, TODE.

Acceleration of EM-Based 3D CT Reconstruction Using FPGA

Jason Cong, Young Kyu Choi, J. Cong, 2016, IEEE Transactions on Biomedical Circuits and Systems.

MC-Sim: an efficient simulation tool for MPSoC designs

Jason Cong, Glenn Reinman, Guoling Han, 2008, ICCAD 2008.

ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures

Jason Cong, Yu-Ting Chen, Bingjun Xiao, 2015, 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

NSF Workshop on EDA: Past, Present, and Future (Part 1)

Robert K. Brayton, Jason Cong, R. Brayton, 2010, IEEE Des. Test Comput..

Accelerating Monte Carlo based SSTA using FPGA

Jason Cong, Bin Liu, Wei Jiang, 2010, FPGA '10.

Impulse response analysis of carrier-modulated multiband RF-interconnect (MRFI)

Jason Cong, Mau-Chung Frank Chang, Tatsuo Itoh, 2017 .

Optimal simultaneous mapping and clustering for FPGA delay optimization

Jason Cong, Deming Chen, Joey Y. Lin, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

An efficient and flexible host-FPGA PCIe communication library

Jason Cong, Songwu Lu, Jian Gong, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Placement and placement driven technology mapping for FPGA synthesis

Jason Cong, Kuang-Chien Chen, Yuzheng Ding, 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.

Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit

Jason Cong, Peipei Zhou, Jie Wang, 2020, 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Are we ready for system-level synthesis?

Jason Cong, Jan M. Rabaey, Kazutoshi Wakabayashi, 2005, ASP-DAC '05.

Logic-on-logic 3D integration and placement

Jason Cong, Paul D. Franzon, Guojie Luo, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Understanding Performance Differences of FPGAs and GPUs

Jason Cong, Zhenman Fang, Jingxian Xu, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Physical hierarchy generation with routing congestion control

Jason Cong, David Z. Pan, Chin-Chih Chang, 2002, ISPD '02.

Improved crosstalk modeling for noise constrained interconnect optimization

Jason Cong, David Z. Pan, Prasanna V. Srinivas, 2001, ASP-DAC '01.

Bonsai: High-Performance Adaptive Merge Tree Sorting

Jason Cong, Mau-Chung Frank Chang, Vaibhav Aggarwal, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

Session details: Evening panel: are FPGAs suffering from the innovator's dilemna?

Jason Cong, 2013, FPGA '13.

Optimality and scalability study of existing placement algorithms

Jason Cong, Min Xie, Chin-Chih Chang, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SODA: Stencil with Optimized Dataflow Architecture

Jason Cong, Peng Wei, Peipei Zhou, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs

Jason Cong, Yu Wang, Sheqin Dong, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Large-scale circuit placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005, TODE.

Incremental Indoor Map Construction with a Single User

Jason Cong, Fan Ye, Guojie Luo, 2018 .

Throughput Optimization for High-Level Synthesis Using Resource Constraints

Jason Cong, Peng Li, 2014 .

Performance driven multi-level and multiway partitioning with retiming

Jason Cong, Sung Kyu Lim, Chang Wu, 2000, Proceedings 37th Design Automation Conference.

General models and algorithms for over-the-cell routing in standard cell design

Jason Cong, C. L. Liu, Bryan Preas, 1991, DAC '90.

Synthesis of an application-specific soft multiprocessor system

Jason Cong, Wei Jiang, Guoling Han, 2007, FPGA '07.

Logic synthesis for better than worst-case designs

Jason Cong, Kirill Minkovich, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA

Jason Cong, Peipei Zhou, Tong He, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

LUT-based FPGA technology mapping under arbitrary net-delay models

Jason Cong, Tong Gao, Kuang-Chien Chen, 1994, Comput. Graph..

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

Jason Cong, Adrian Tang, Mau-Chung Frank Chang, 2012, 2012 IEEE International Solid-State Circuits Conference.

Incremental CAD

Jason Cong, Olivier Coudert, Sharad Malik, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Application-specific instruction generation for configurable processor architectures

Jason Cong, Zhiru Zhang, Yiping Fan, 2004, FPGA '04.

Domain-specific processor with 3D integration for medical image processing

Jason Cong, Muhuan Huang, Sen Li, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network

Jason Cong, Wen Gao, Xiaodong Xie, 2020, IEEE Transactions on Medical Imaging.

FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation

Jason Cong, Peng Li, Pei Wang, 2014, FCCM 2014.

HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA

Jason Cong, Miryung Kim, Qian Zhang, 2020, 2020 IEEE/ACM 42nd International Conference on Software Engineering (ICSE).

Thermal-Aware 3D Placement

Jason Cong, Guojie Luo, J. Cong, 2010 .

Resolving implicit barrier synchronizations in FPGA HLS (abstract only)

Jason Cong, Yi Zou, 2011, FPGA '11.

Retiming-based timing analysis with an application to mincut-based global placement

Jason Cong, Sung Kyu Lim, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale

Jason Cong, Zhenman Fang, Cody Hao Yu, 2016, SoCC.

Technology mapping for FPGAs with nonuniform pin delays and fast interconnections

Jason Cong, Songjie Xu, Yean-Yow Hwang, 1999, DAC '99.

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering

Jason Cong, Sung Kyu Lim, Toshiyuki Shibuya, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

High-performance vlsi global routing

Jason Cong, Patrick H. Madden, J. Cong, 1998 .

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

Jason Cong, Jongsun Kim, Mau-Chung Frank Chang, 2011, 2011 IEEE International Solid-State Circuits Conference.

On High-Speed VLSI Interconnects: Analysis and Design

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung, 1992 .

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999

Jason Cong, David Blaauw, Farid N. Najm, 1999, International Symposium on Low Power Electronics and Design.

An FPGA-Based BWT Accelerator for Bzip2 Data Compression

Jason Cong, Zhenman Fang, Mau-Chung Frank Chang, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases

Tao Zhang, Jason Cong, Yiran Chen, 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Microarchitecture evaluation with floorplanning and interconnect pipelining

Jason Cong, Glenn Reinman, Michail Romesis, 2005, ASP-DAC.

Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU

Jason Cong, Peng Wei, Zhenyuan Ruan, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

A fast multilayer general area router for MCM designs

Jason Cong, Kei-Yong Khoo, 1992, EURO-DAC '92.

Editorial: Special issue on 3D integrated circuits and microarchitectures

Jason Cong, Yuan Xie, Paul D. Franzon, 2008, JETC.

Interconnect estimation and planning for deep submicron designs

Jason Cong, David Z. Pan, 1999, DAC '99.

A Robust Mixed-Size Legalization and Detailed Placement Algorithm

Jason Cong, Min Xie, J. Cong, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimality and scalability study of existing placement algorithms

Jason Cong, Min Xie, Chin-Chih Chang, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping

Jason Cong, Yean-Yow Hwang, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Thermal-aware cell and through-silicon-via co-placement for 3D ICs

Jason Cong, Yiyu Shi, Guojie Luo, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only)

Jason Cong, Yunsong Li, Jie Lei, 2016, FPGA.

Simultaneous Driver And Wire Sizing For Performance And Power Optimization*

Jason Cong, Cheng-Kok Koh, J. Cong, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Indoor Map Construction via Mobile Crowdsensing

Jason Cong, Fan Ye, Guojie Luo, 2018 .

A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis

Jason Cong, Román Hermida, Alberto A. Del Barrio, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Behavior-level observability don't-cares and application to low-power behavioral synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2009, ISLPED.

Interconnect synthesis of heterogeneous accelerators in a shared memory architecture

Jason Cong, Yu-Ting Chen, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices

Jason Cong, Zhe Chen, Hugh T. Blair, 2018, ISLPED.

Random walks for circuit clustering

Jason Cong, Andrew B. Kahng, L. Hagen, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Efficient compilation of CUDA kernels for high-performance computing on FPGAs

Jason Cong, Deming Chen, Wen-mei W. Hwu, 2013, TECS.

Moore's Law: Another casualty of the financial meltdown?

Jason Cong, Riko Radojcic, Ruchir Puri, 2009, 2009 46th ACM/IEEE Design Automation Conference.

DAG-Map: graph-based FPGA technology mapping for delay optimization

Jason Cong, Andrew B. Kahng, Kuang-Chien Chen, 1992, IEEE Design & Test of Computers.

Fast floorplanning by look-ahead enabled recursive bipartitioning

Joseph R. Shinnerl, Jason Cong, Michail Romesis, 2005, ASP-DAC.

A new formulation of yield enhancement problems for reconfigurable chips

Jason Cong, Nany Hasan, C. L. Liu, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Synthesis of reconfigurable high-performance multicore systems

Jason Cong, Guoling Han, Karthik Gururaj, 2009, FPGA '09.

Coupling Of Synthesis And Layout: Challenges And Solutions

Jason Cong, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A 125GHz transceiver in 65nm CMOS assembled with FR4 PCB antenna for contactless wave-connectors

Jason Cong, Mau-Chung Frank Chang, Yan Zhao, 2017, 2017 IEEE MTT-S International Microwave Symposium (IMS).

Global interconnect sizing and spacing with consideration of coupling capacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Scaling for edge inference of deep neural networks

Jason Cong, Yiyu Shi, Michael Niemier, 2018 .

xPilot: A Platform-Based Behavioral Synthesis System

Jason Cong, Zhiru Zhang, Deming Chen, 2005 .

Minimum Density Interconneciton Trees

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1993, ISCAS.

Enhancing Placement with Multilevel Techniques

Joseph R. Shinnerl, Jason Cong, 2008, Handbook of Algorithms for Physical Design Automation.

Challenges and Opportunities for Design Innovations in Nanometer Technologies

Jason Cong, J. Cong, 1998 .

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers

Jason Cong, Peng Li, Peng Zhang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only)

Jason Cong, Jie Wang, 2015, FPGA.

Extending High-Level Synthesis for Task-Parallel Programs pdf

Jason Cong, Jie Wang, Young-kyu Choi, 2020, ArXiv.

A metric for layout-friendly microarchitecture optimization in high-level synthesis

Jason Cong, Bin Liu, J. Cong, 2012, DAC Design Automation Conference 2012.

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Jason Cong, Yuzheng Ding, 1992, ICCAD.

Performance optimization of VLSI interconnect layout

Jason Cong, Cheng-Kok Koh, Lei He, 1996, Integr..

InterFS: An Interplanted Distributed File System to Improve Storage Utilization

Jason Cong, Guangyu Sun, Peng Wang, 2015, APSys.

Cubic Packing with Various Candidates for 3D IC Design

Jason Cong, Zhuoyuan Li, Sheqin Dong, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

When apache spark meets FPGAs: a case study for next-generation DNA sequencing acceleration

Jason Cong, Zhenman Fang, Jie Lei, 2016, CloudCom 2016.

A 3D physical design flow based on Open Access

Jason Cong, Guojie Luo, J. Cong, 2009, 2009 International Conference on Communications, Circuits and Systems.

Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application

Faming Liang, Jason Cong, Wing Hung Wong, 2000, ASP-DAC '00.

Optimal wiresizing for interconnects with multiple sources

Jason Cong, Lei He, 1995, TODE.

DUNE-a multilayer gridless routing system

Jason Cong, Jie Fang, Kei-Yong Khoo, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

mPL6: enhanced multilevel mixed-size placement

Joseph R. Shinnerl, Jason Cong, Min Xie, 2006, ISPD '06.

ATree-based topology synthesis for on-chip network

Jason Cong, Bo Yuan, Yuhui Huang, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications

Jason Cong, Jongchan Park, Jeonghun Kim, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application

Faming Liang, Jason Cong, Wing Hung Wong, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Optimal wiresizing under the distributed Elmore delay model

Jason Cong, Kwok-Shing Leung, J. Cong, 1993, ICCAD '93.

An interconnect energy model considering coupling effects

Jason Cong, Taku Uchino, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Optimizing routability in large-scale mixed-size placement

Jason Cong, Guojie Luo, Bingjun Xiao, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Multilevel approach to full-chip gridless routing

Jason Cong, Jie Fang, VI YanZhang, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Interconnect performance estimation models for design planning

Jason Cong, David Z. Pan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Mapping for better than worst-case delays in LUT-based FPGA designs

Jason Cong, Kirill Minkovich, J. Cong, 2008, FPGA '08.

Instruction set extension with shadow registers for configurable processors

Jason Cong, Zhiru Zhang, Glenn Reinman, 2005, FPGA '05.

Interconnect layout optimization under higher-order RLC model

Jason Cong, Cheng-Kok Koh, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A thermal-driven floorplanning algorithm for 3D ICs

Jason Cong, Yan Zhang, Jie Wei, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Coordinated resource optimization in behavioral synthesis

Jason Cong, Bin Liu, Junjuan Xu, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

The Last Byte: The HLS tipping point

Jason Cong, Wolfgang Rosenstiel, 2009, IEEE Design & Test of Computers.

Multi-way VLSI circuit partitioning based on dual net representation

Jason Cong, Wilburt Labio, Narayanan Shivakumar, 1994, ICCAD.

Bandwidth optimization through on-chip memory restructuring for HLS

Jason Cong, Peng Wei, Cody Hao Yu, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation

Jason Cong, Peng Li, Ming Jiang, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

FPGA Design Automation: A Survey

Jason Cong, Deming Chen, Peichen Pan, 2006, Found. Trends Electron. Des. Autom..

Interconnect synthesis and planning for high-performance ic designs

Jason Cong, Zhigang Pan, 2000 .

Technology mapping for k/m-macrocell based FPGAs

Jason Cong, Xin Yuan, Hui Huang, 2000, FPGA '00.

A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design

Jason Cong, M'Lissa Smith, J. Cong, 1993, 30th ACM/IEEE Design Automation Conference.

Session details: Physical design

Jason Cong, 2008, FPGA '08.

Intellectual property protection by watermarking combinational logic synthesis solutions

Jason Cong, Miodrag Potkonjak, Darko Kirovski, 1998, ICCAD '98.

A new enhanced SPFD rewiring algorithm [logic IC layout]

Jason Cong, Joey Y. Lin, Wangning Long, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

Jason Cong, Chang Wu, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

An efficient approach to multi-layer layer assignment with application to via minimization

Jason Cong, Chin-Chih Chang, 1997, DAC.

Three Dimensional Integrated Circuit Design

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2010 .

FPGA Implementation of EM Algorithm for 3D CT Reconstruction

Jason Cong, Di Wu, Young-kyu Choi, 2014, FCCM 2014.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms

Jason Cong, Zhenman Fang, Yuchen Hao, 2019, ACM Trans. Reconfigurable Technol. Syst..

Chapter 13 – Technology Mapping

Jason Cong, 2008 .

Multiway VLSI circuit partitioning based on dual net representation

Jason Cong, Wilburt Labio, Narayanan Shivakumar, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient approach to multilayer layer assignment with anapplication to via minimization

Jason Cong, Chin-Chih Chang, J. Cong, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Understanding the energy efficiency of SMT and CMP with multiclustering

Jason Cong, Glenn Reinman, Yuval Tamir, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

The Supercomputer Supernet: A Scalable Distributed Terabit Network

Jason Cong, Nicholas Bambos, Eli Gafni, 1995, J. High Speed Networks.

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Jason Cong, Takumi Okamoto, 1996, ICCAD 1996.

RASP: A General Logic Synthesis System for SRAM-Based FPGAs

Jason Cong, John Peck, Yuzheng Ding, 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

Jason Cong, Yuzheng Ding, 1993, 30th ACM/IEEE Design Automation Conference.

A fast four-via multilayer MCM router

Jason Cong, K.-Y. Khoo, 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.

Robust mixed-size placement under tight white-space constraints

Joseph R. Shinnerl, Jason Cong, Michail Romesis, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Composable accelerator-rich microprocessor enhanced for adaptivity and longevity

Jason Cong, Glenn Reinman, Hui Huang, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

LUT-based FPGA technology mapping for reliability (abstract only)

Jason Cong, Kirill Minkovich, 2010, FPGA '10.

A unified optimization framework for simultaneous gate sizing and placement under density constraints

Jason Cong, Guojie Luo, John Lee, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Architecture evaluation for power-efficient FPGAs

Jason Cong, Fei Li, Lei He, 2003, FPGA '03.

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Zhiru Zhang, Bin Liu, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Transformations for throughput optimization in high-level synthesis (abstract only)

Jason Cong, Peng Li, Deming Chen, 2014, FPGA.

Memory partitioning for multidimensional arrays in high-level synthesis

Jason Cong, Peng Li, Chen Zhang, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis pdf

Jason Cong, Zhenman Fang, Peng Wei, 2016, ArXiv.

Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures

Jason Cong, Sachin S. Sapatnekar, Yuan Xie, 2009 .

How will CAD handle billion-transistor systems? (panel)

Jason Cong, Wayne Wolf, Ken Shepard, 1998, ICCAD '98.

Mapping a data-flow programming model onto heterogeneous platforms

Jason Cong, Vivek Sarkar, Yi Zou, 2012, LCTES 2012.

Energy-efficient scheduling on heterogeneous multi-core architectures

Jason Cong, Bo Yuan, J. Cong, 2012, ISLPED '12.

A Comparative Study on the Architecture Templates for Dynamic Nested Loops

Jason Cong, Yi Zou, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

Customizable Domain-Specific Computing

Jason Cong, Vivek Sarkar, Alex A. T. Bui, 2009, IEEE Design & Test of Computers.

An automated design flow for 3D microarchitecture evaluation

Jason Cong, Yan Zhang, Jie Wei, 2006, Asia and South Pacific Conference on Design Automation, 2006..

From design to design automation

Jason Cong, 2014, ISPD '14.

Optimal wiresizing under Elmore delay model

Jason Cong, Kwok-Shing Leung, J. Cong, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

PARADE: A cycle-accurate full-system simulation Platform for Accelerator-Rich Architectural Design and Exploration

Jason Cong, Zhenman Fang, Glenn Reinman, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

Jason Cong, Yean-Yow Hwang, 1996, DAC '96.

Multilevel optimization for large-scale circuit placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

A new generation of C-base synthesis tool and domain-specific computing

Jason Cong, 2008, 2008 IEEE International SOC Conference.

On the k-layer planar subset and via minimization problems

Jason Cong, C. L. Liu, J. Cong, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Jason Cong, Takumi Okamoto, 1996, Proceedings of International Conference on Computer Aided Design.

General Formulation of Fault Covering Problems

Jason Cong, Ran Libeskind-Hadas, Nany Hasan, 1992 .

Architecture support for custom instructions with memory operations

Jason Cong, Karthik Gururaj, 2013, FPGA '13.

Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors

Jason Cong, Zhiru Zhang, Guoling Han, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis techniques for application-specific processor-based design

Jason Cong, Guoling Han, 2007 .

Accelerating Sequential Applications on CMPs Using Core Spilling

Jason Cong, Glenn Reinman, Krzysztof Rutkowski, 2007, IEEE Transactions on Parallel and Distributed Systems.

Customizable Computing—From Single Chip to Datacenters

Jason Cong, Zhenman Fang, Peng Wei, 2019, Proceedings of the IEEE.

Delay-optimal technology mapping for FPGAs with heterogeneous LUTs

Jason Cong, Songjie Xu, J. Cong, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Locality and Utilization in Placement Suboptimality

Joseph R. Shinnerl, Jason Cong, Min Xie, 2007, Modern Circuit Placement.

Technology mapping for FPGAs with embedded memory blocks

Jason Cong, Songjie Xu, J. Cong, 1998, FPGA '98.

Performance-driven fpga synthesis for sequential circuits

Jason Cong, Chang Wu, 1999 .

An efficient multilayer MCM router based on four-via routing

Jason Cong, Kei-Yong Khoo, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Interconnect delay estimation models for synthesis and design planning

Jason Cong, David Z. Pan, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Platform-based resource binding using a distributed register-file microarchitecture

Jason Cong, Wei Jiang, Yiping Fan, 2006, ICCAD.

Intellectual property protection by watermarking combinational logic synthesis solutions

Jason Cong, Miodrag Potkonjak, Darko Kirovski, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Performance-Driven Interconnect Design Based on Distributed RC Delay Model

Jason Cong, Kwok-Shing Leung, Dian Zhou, 1993, 30th ACM/IEEE Design Automation Conference.

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ICCAD 2003.

Automating customized computing

Jason Cong, 2014, FPT.

Relaxed simulated tempering for VLSI floorplan designs

Faming Liang, Jason Cong, Wing Hung Wong, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Simultaneous driver and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, 1994, ICCAD.

Minimum-cost bounded-skew clock routing

Jason Cong, Cheng-Kok Koh, J. Cong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration

Jason Cong, Zhenman Fang, Peng Wei, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

S2FA: an accelerator automation framework for heterogeneous computing in datacenters

Peng Zhang, Jason Cong, Peng Wei, 2018, DAC.

Placement and design planning for three-dimensional integrated circuits

Jason Cong, Guojie Luo, 2011 .

Overview of Center for Domain-Specific Computing

Jason Cong, 2011, Journal of Computer Science and Technology.

A Fast Multila er General Area Router for hCM Designs

Jason Cong, Kei-Yong Khoo, 1992 .

MC-Sim: An efficient simulation tool for MPSoC designs

Jason Cong, Glenn Reinman, Guoling Han, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction

Jason Cong, Ming Yan, Jianwen Chen, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

for Delay Optimization

Jason Cong, Andrew B. Kahng, Los Angeles, 1992 .

DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Jason Cong, Deming Chen, 2004, ICCAD 2004.

Buffer block planning for interconnect planning and prediction

Jason Cong, Tianming Kong, Z. D. Pan, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998

Jason Cong, Sinan Kaptanoglu, J. Cong, 1998, FPGA.

Introduction of Indoor Map Construction

Jason Cong, Fan Ye, Guojie Luo, 2018 .

Scheduling with integer time budgeting for low-power optimization

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Growing a Healthy FPGA Ecosystem

Jason Cong, Derek Chiou, Michael Adler, 2015, FPGA.

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

Jason Cong, Cody Hao Yu, Zhe Chen, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Accelerating vision and navigation applications on a customizable platform

Jason Cong, Glenn Reinman, Beayna Grigorian, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs

Jason Cong, Satoshi Goto, Sheqin Dong, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

A multilevel analytical placement for 3D ICs

Jason Cong, Guojie Luo, J. Cong, 2009, 2009 Asia and South Pacific Design Automation Conference.

LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization

Jason Cong, Zhe Chen, Hugh T. Blair, 2019, FPGA.

Protecting Combinational Logic Synthesis Solutions

Jason Cong, Miodrag Potkonjak, Darko Kirovski, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SRC 1091.001 Final Deliverable Report for Oct 2006: Highly Scalable Multilevel Placement Algorithm for Mixed-size with Complex Constraints

Joseph R. Shinnerl, Jason Cong, Min Xie, 2006 .

Physical models and efficient algorithms for over-the-cell routing in standard cell design

Jason Cong, C. L. Liu, Bryan Preas, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault tolerant placement and defect reconfiguration for nano-FPGAs

Jason Cong, Amit Agarwal, Brian Tagiku, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms

Jason Cong, Zhenman Fang, Mau-Chung Frank Chang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only)

Jason Cong, Songwu Lu, Jian Gong, 2014, FPGA.

Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Multiband RF-interconnect for reconfigurable network-on-chip communications

Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, 2009, SLIP '09.

Indoor Localization by Photo-Taking of the Environment

Jason Cong, Fan Ye, Guojie Luo, 2018 .

Fault tolerant placement and defect reconfiguration for nano-FPGAs

Jason Cong, Brian Tagiku, Amit Kumar Agarwal, 2008, ICCAD 2008.

Resource-Aware Throughput Optimization for High-Level Synthesis

Jason Cong, Peng Li, Peng Zhang, 2015, FPGA.

Performance driven multiway partitioning

Jason Cong, Sung Kyu Lim, 2000, ASP-DAC.

Multiway partitioning with pairwise movement

Jason Cong, Sung Kyu Lim, 1998, ICCAD.

Minimizing Computation in Convolutional Neural Networks

Jason Cong, Bingjun Xiao, J. Cong, 2014, ICANN.

A new enhanced SPFD rewiring algorithm

Jason Cong, Joey Y. Lin, Wangning Long, 2002, ICCAD 2002.

Compiler transformations for electronic system level synthesis

Jason Cong, Wei Jiang, 2009 .

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration

Jason Cong, Yuze Chi, Jiajie Li, 2020, FPGA.

Performance-driven technology mapping for heterogeneous FPGAs

Jason Cong, Songjie Xu, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

CHARM: a composable heterogeneous accelerator-rich microprocessor

Jason Cong, Glenn Reinman, Michael Gill, 2012, ISLPED '12.

Pattern-Mining for Behavioral Synthesis

Jason Cong, Wei Jiang, Hui Huang, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Source-to-Source Optimization for HLS

Jason Cong, Peng Zhang, Yuxin Wang, 2016, FPGAs for Software Programmers.

Exploiting signal flow and logic dependency in standard cell placement

Jason Cong, Dongmin Xu, 1995, ASP-DAC '95.

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Jason Cong, Yuzheng Ding, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An area-optimality study of floorplanning

Joseph R. Shinnerl, Jason Cong, Michail Romesis, 2004, ISPD '04.

Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects

Jason Cong, Hao Wu, Mau-Chung Frank Chang, 2013, TACO.

Understanding Performance Differences of FPGAs and GPUs: (Abtract Only)

Jason Cong, Zhenman Fang, Jingxian Xu, 2018, FPGA.

Defect tolerance in nanodevice-based programmable interconnects: Utilization beyond avoidance

Jason Cong, Bingjun Xiao, J. Cong, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Net partitions yield better module partitions

Jason Cong, Andrew B. Kahng, Lars W. Hagen, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Performance-driven multi-level clustering with application to hierarchical FPGA mapping

Jason Cong, Michail Romesis, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

CPU-FPGA Coscheduling for Big Data Applications

Jason Cong, Zhenman Fang, Muhuan Huang, 2018, IEEE Design & Test.

Gradual Relaxation Techniques with Applications to Behavioral Synthesis

Jason Cong, Miodrag Potkonjak, Zhiru Zhang, 2003, ICCAD.

Performance driven multi-layer general area routing for PCB/MCM designs

Jason Cong, Patrick H. Madden, J. Cong, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization pdf

Jason Cong, Jie Wang, Young-kyu Choi, 2020, ArXiv.

A rigorous framework for convergent net weighting schemes in timing-driven placement

Jason Cong, Tony F. Chan, Eric Radke, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Performance driven routing with multiple sources

Jason Cong, Patrick H. Madden, J. Cong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Era of customization and specialization

Jason Cong, 2011, ASAP.

The SMEM Seeding Acceleration for DNA Sequence Alignment

Jason Cong, Cody Hao Yu, Mau-Chung Frank Chang, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Supercomputer Supernet (SSN): a high-speed electro-optic campus and metropolitan network

Jason Cong, John Peck, Nicholas Bambos, 1996, Photonics West.

Via design rule consideration in multilayer maze routing algorithms

Jason Cong, Jie Fang, Kei-Yong Khoo, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient algorithm for performance-optimal FPGA technology mapping with retiming

Jason Cong, Chang Wu, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs

Jason Cong, Songjie Xu, 2000, ASP-DAC '00.

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Jason Cong, Miodrag Potkonjak, Bin Liu, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

DUNE: a multi-layer gridless routing system with wire planning

Jason Cong, Jie Fang, Kei-Yong Khoo, 2000, ISPD '00.

Advances and Challenges in 3D Physical Design

Jason Cong, Guojie Luo, J. Cong, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

AutoPilot: A Platform-Based ESL Synthesis System

Jason Cong, Zhiru Zhang, Yiping Fan, 2008 .

A robust detailed placement for mixed-size IC designs

Jason Cong, Min Xie, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Thermal-Aware 3D IC Placement Via Transformation

Jason Cong, Yan Zhang, Jie Wei, 2007, 2007 Asia and South Pacific Design Automation Conference.

Parallel multi-level analytical global placement on graphics processing units

Jason Cong, Yi Zou, J. Cong, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Lower-bound estimation for multi-bitwidth scheduling

Jason Cong, Xu Cheng, Junjuan Xu, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Session details: New CAD techniques and methods

Jason Cong, 2005, FPGA '05.

High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms

Jason Cong, Zhenman Fang, Mau-Chung Frank Chang, 2018, FCCM.

Acyclic Multi-Way Partitioning of Boolean Networks

Jason Cong, Zheng Li, Rajive L. Bagrodia, 1994, 31st Design Automation Conference.

An efficient approach to simultaneous transistor and interconnect sizing

Jason Cong, Lei He, 1996, ICCAD 1996.

Multilevel Optimization in VLSICAD

Joseph R. Shinnerl, Jason Cong, J. Cong, 2003 .

Microarchitecture evaluation with physical planning

Jason Cong, Glenn Reinman, Michail Romesis, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Zhiru Zhang, Wei Jiang, 2006, 2006 IEEE International SOC Conference.

Placement-driven technology mapping for LUT-based FPGAs

Jason Cong, Joey Y. Lin, Ashok Jagannathan, 2003, FPGA '03.

State of the Journal

Jason Cong, Dinesh Manocha, Sushil Jajodia, 2016, IEEE Trans. Computers.

How will CAD handle billion-transistor systems? (panel)

Jason Cong, Kenneth L. Shepard, Robert C. Aitken, 1998, International Conference on Computer Aided Design.

Multi-level placement for large-scale mixed-size IC designs

Jason Cong, Xin Yuan, Chin-Chih Chang, 2003, ASP-DAC '03.

Impact of loop transformations on software reliability

Jason Cong, Cody Hao Yu, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses

Jason Cong, Guangyu Sun, Nong Xiao, 2019, IEEE Transactions on Computers.

Conclusion and Challenges

Jason Cong, Gi-Joon Nam, 2007, Modern Circuit Placement.

Lithographic aerial image simulation with FPGA-based hardwareacceleration

Jason Cong, Yi Zou, 2008, FPGA '08.

IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

Jason Cong, Ronald Tetzlaff, Gert Cauwenberghs, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Multilevel generalized force-directed method for circuit placement

Jason Cong, Tony F. Chan, Kenton Sze, 2005, ISPD '05.

Buffer block planning for interconnect-driven floorplanning

Jason Cong, David Z. Pan, Tianming Kong, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs

Jason Cong, Zhiru Zhang, Deming Chen, 2007, 2007 Asia and South Pacific Design Automation Conference.

A scalable, high-performance customized priority queue

Jason Cong, Muhuan Huang, Kevin Lim, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Synthesis challenges for next-generation high-performance and high-density PLDs

Jason Cong, Songjie Xu, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation

Jason Cong, Yean-Yow Hwang, 1998, FPGA '98.

Multilevel global placement with retiming

Jason Cong, Xin Yuan, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Defect recovery in nanodevice-based programmable interconnects (abstract only)

Jason Cong, Bingjun Xiao, 2013, FPGA '13.

Accelerator-rich architectures: Opportunities and progresses

Jason Cong, Glenn Reinman, Karthik Gururaj, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Novel techniques for large-scale circuit placement

Jason Cong, Tianming Kong, 2002 .

The survivability of design-specific spare placement in FPGA architectures with high defect rates

Jason Cong, Amit Agarwal, Brian Tagiku, 2013, TODE.

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Jason Cong, Yuzheng Ding, 1992, ICCAD 1992.

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Jason Cong, Bingjun Xiao, J. Cong, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory

Jason Cong, Zhenman Fang, Glenn Reinman, 2017, MEMSYS.

Edge separability-based circuit clustering with application to multilevel circuit partitioning

Jason Cong, Sung Kyu Lim, J. Cong, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Highly Efficient Gradient Computation for Density-Constrained Analytical Placement

Jason Cong, Guojie Luo, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, ICCAD.

On Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors

Jason Cong, John Peck, 1997 .

High-performance CUDA kernel execution on FPGAs

Jason Cong, Deming Chen, Wen-mei W. Hwu, 2009, ICS.

Wiresizing with Driver Sizing for Performance and Power Optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1994 .

Architecture and synthesis for on-chip multicycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Over-the-cell channel routing

Jason Cong, C. L. Liu, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive

Jason Cong, Tong He, Zhenyuan Ruan, 2019, USENIX Annual Technical Conference.

Performance-driven mapping for CPLD architectures

Jason Cong, Milos D. Ercegovac, Deming Chen, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Nosie and signal integrity in deep submicron design (panel)

Jason Cong, Rakesh Chadha, Anirudh Devgan, 1997, DAC 1997.

EM+TV for Reconstruction of Cone-beam CT with Curved Detectors using GPU

Jason Cong, Ming Yan, Alex A. T. Bui, 2011 .

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing

Jason Cong, Cody Hao Yu, Yuan Zhou, 2019, FPGA.

An efficient approach to simultaneous transistor and interconnect sizing

Jason Cong, Lei He, 1996, Proceedings of International Conference on Computer Aided Design.

A provable near-optimal algorithm for the channel pin assignment problem

Jason Cong, Kei-Yong Khoo, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A Study on the Impact of Compiler Optimizations on High-Level Synthesis

Jason Cong, Bin Liu, Peng Zhang, 2012, LCPC.

Vlsi interconnect layout optimization

Jason Cong, Cheng-Kok Koh, 1998 .

An interconnect energy model considering coupling effects

Jason Cong, Taku Uchino, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

What happened to ASIC?: Go (recon)figure?

Jason Cong, Ivo Bolsens, Chris Rowen, 2004, DAC '04.

Robust gate sizing via mean excess delay minimization

Jason Cong, Lieven Vandenberghe, John Lee, 2008, ISPD '08.

An enhanced multilevel algorithm for circuit placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms

Jason Cong, Jie Wang, Xinfeng Xie, 2017, 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms

Jason Cong, Muhuan Huang, Yi Zou, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ICCAD.

An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy

Jason Cong, Alex A. T. Bui, William Hsu, 2015, Comput. Biol. Medicine.

Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Hierarchical Cl

Jason Cong, Sung Kyu Lim, Toshiyuki Shibuya, 1997, ICCAD 1997.

GRT: A Reconfigurable SDR Platform with High Performance and Usability

Jason Cong, Songwu Lu, Guangyu Sun, 2014, CARN.

Physical planning with retiming

Jason Cong, Sung Kyu Lim, J. Cong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Combining computation and communication optimizations in system synthesis for streaming applications

Jason Cong, Peng Zhang, Muhuan Huang, 2014, FPGA.

Design and synthesis for low-power fpgas

Jason Cong, Deming Chen, 2005 .

FPGA Technology Mapping

Jason Cong, Yuzheng Ding, 2008, Encyclopedia of Algorithms.

HLS-Based Optimization and Design Space Exploration for Applications with Variable Loop Bounds

Jason Cong, Young-kyu Choi, J. Cong, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Large-Scale Circuit Placement: Gap and Promise

Joseph R. Shinnerl, Jason Cong, Min Xie, 2003, ICCAD 2003.

A scalable communication-aware compilation flow for programmable accelerators

Jason Cong, Hui Huang, Mohammad Ali Ghodrat, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

Jason Cong, Chang Wu, 1997, DAC.

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Jason Cong, Fei Li, Lei He, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High-performance clock routing based on recursive geometric matching

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1991, 28th ACM/IEEE Design Automation Conference.

Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis

Jason Cong, Zhiru Zhang, Bin Liu, 2010, TODE.

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Jason Cong, Chen Zhang, Yijin Guan, 2015, FPGA.

Combined loop transformation and hierarchy allocation for data reuse optimization

Jason Cong, Peng Zhang, Yi Zou, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

"High-level synthesis and beyond - From datacenters to IoTs"

Jason Cong, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Pseudo pin assignment with crosstalk noise control

Jason Cong, Chin-Chih Chang, J. Cong, 2000, ISPD '00.

Scheduling with soft constraints

Jason Cong, Zhiru Zhang, Bin Liu, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

A new algorithm for standard cell global routing

Jason Cong, Bryan Preas, 1992, Integr..

CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time

Jason Cong, Zhe Chen, Hugh T. Blair, 2020, FPGA.

Modeling and layout optimization of VLSI devices and interconnects in deep submicron design

Jason Cong, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only)

Jason Cong, Peng Li, Chen Zhang, 2013, FPGA '13.

Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

Jason Cong, Chang Wu, Yuzheng Ding, 1999, FPGA '99.

Routing tree construction under fixed buffer locations

Jason Cong, Xin Yuan, J. Cong, 2000, Proceedings 37th Design Automation Conference.

On clock routing for general cell layouts

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning

Jason Cong, Qiang Zhou, Zhuoyuan Li, 2007, 2007 Asia and South Pacific Design Automation Conference.

Parallelization, Customization and Automation

Jason Cong, 2012 .

Supporting Address Translation for Accelerator-Centric Architectures

Jason Cong, Yuchen Hao, Glenn Reinman, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Optimality Study of Logic Synthesis for LUT-Based FPGAs

Jason Cong, Kirill Minkovich, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining

Jason Cong, Peng Wei, Cody Hao Yu, 2018, HotCloud.

On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

Jason Cong, John Peck, 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

A variation-tolerant scheduler for better than worst-case behavioral synthesis

Jason Cong, Bin Liu, Albert Liu, 2009, CODES+ISSS '09.

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only)

Jason Cong, Zhenman Fang, Peipei Zhou, 2016, FPGA.

FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects

Jason Cong, Bingjun Xiao, J. Cong, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing

Jason Cong, Po-Tsang Huang, Tianhe Yu, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Depth optimal incremental mapping for field programmable gate arrays

Jason Cong, Hui Huang, 2000, DAC.

RF-Interconnect for Future Network-On-Chip

Jason Cong, Mau-Chung Frank Chang, Eran Socher, 2011, Low Power Networks-on-Chip.

Revisiting bitwidth optimizations

Jason Cong, Zhiru Zhang, Bin Liu, 2009, FPGA '09.

Multilevel global placement with congestion control

Jason Cong, David Z. Pan, Xin Yuan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, ICCAD 2004.

Invited: Heterogeneous datacenters: Options and opportunities

Jason Cong, Cody Hao Yu, Di Wu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Fine grain 3D integration for microarchitecture design through cube packing exploration

Jason Cong, Glenn Reinman, Yuchun Ma, 2007, 2007 25th International Conference on Computer Design.

Jason Cong, Deming Chen, 2004 .

Power reduction of CMP communication networks via RF-interconnects

Jason Cong, Mau-Chung Frank Chang, Eran Socher, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA

Jason Cong, Yean-Yow Hwang, 1995 .

Scaling Up Physical Design: Challenges and Opportunities

Jason Cong, Guojie Luo, Jiaxi Zhang, 2016, ISPD.

Power modeling and characteristics of field programmable gate arrays

Jason Cong, Fei Li, Lei He, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Minimum density interconnection trees

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Multilevel routing for a higher degree of circuit integration

Jason Cong, Yan Zhang, 2006 .

Maximal reduction of lookup-table based FPGAs

Jason Cong, Kuang-Chien Chen, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Large-Scale Global Placement

Joseph R. Shinnerl, Jason Cong, J. Cong, 2007, Handbook of Approximation Algorithms and Metaheuristics.

Thermal via planning for 3-D ICs

Jason Cong, Yan Zhang, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing

Jason Cong, Peng Wei, Po-Tsang Huang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

MARS-a multilevel full-chip gridless routing system

Jason Cong, Yan Zhang, Min Xie, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Customizable Computing

Jason Cong, Glenn Reinman, Yu-Ting Chen, 2015, Customizable Computing.

Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture pdf

Peng Zhang, Jason Cong, Peng Wei, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

Jason Cong, Deming Chen, Alexandros Papakonstantinou, 2009, 2009 IEEE 7th Symposium on Application Specific Processors.

High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis

Peng Zhang, Jason Cong, Wen Gao, 2015, 2015 IEEE International Conference on Consumer Electronics (ICCE).

Matching-based methods for high-performance clock routing

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Architecture and synthesis for multi-cycle on-chip communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

A fast multilayer general area router for MCM designs

Jason Cong, Kei-Yong Khoo, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Multilevel VLSI Routing

Jason Cong, Min Xie, Yan Zhang, 2003 .

A two-pole circuit model for VLSI high-speed interconnection

Jason Cong, D. S. Gao, Dian Zhou, 1993, 1993 IEEE International Symposium on Circuits and Systems.

NSF Workshop on EDA: Past, Present, and Future (Part 2)

Robert K. Brayton, Jason Cong, R. Brayton, 2010, IEEE Design & Test of Computers.

Synthesis Algorithm for Application-Specific Homogeneous Processor Networks

Jason Cong, Wei Jiang, Guoling Han, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CMP network-on-chip overlaid with multi-band RF-interconnect

Jason Cong, Eran Socher, Glenn Reinman, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Architecture and compilation for data bandwidth improvement in configurable embedded processors

Jason Cong, Zhiru Zhang, Guoling Han, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Automatic memory partitioning and scheduling for throughput and power optimization

Jason Cong, Bin Liu, Wei Jiang, 2011, TODE.

FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)

Jason Cong, Bingjun Xiao, J. Cong, 2012, FPGA '12.

Platform characterization for Domain-Specific Computing

Jason Cong, Kwang-Ting Cheng, Alex A. T. Bui, 2012, 17th Asia and South Pacific Design Automation Conference.

Simultaneous timing-driven placement and duplication

Jason Cong, Gang Chen, 2005, FPGA '05.

On-chip interconnection network for accelerator-rich architectures

Jason Cong, Yuchen Hao, Glenn Reinman, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Simultaneous Timing Driven Clustering and Placement for FPGAs

Jason Cong, Gang Chen, J. Cong, 2004, FPL.

Architecture-level synthesis for automatic interconnect pipelining

Jason Cong, Zhiru Zhang, Yiping Fan, 2004, Proceedings. 41st Design Automation Conference, 2004..

K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only)

Jason Cong, Zhenman Fang, Di Wu, 2018, FPGA.

Architecture Support for Domain-Specific Accelerator-Rich CMPs

Jason Cong, Glenn Reinman, Michael Gill, 2014, ACM Trans. Embed. Comput. Syst..

Optimality study of resource binding with multi-Vdds

Jason Cong, Deming Chen, Yiping Fan, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Performance-driven routing with multiple sources

Jason Cong, Patrick H. Madden, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SPFD-based global rewiring

Jason Cong, Wangning Long, Yizhou Lin, 2002, FPGA '02.

Simultaneous circuit partitioning/clustering with retiming for performance optimization

Jason Cong, Chang Wu, Honching Li, 1999, DAC '99.

On nominal delay minimization in LUT-based FPGA technology mapping

Jason Cong, Yuzheng Ding, 1994, Integr..

Architecture and synthesis for multi-cycle communication

Jason Cong, Zhiru Zhang, Xun Yang, 2003, ISPD '03.

Are FPGAs suffering from the innovator's dilemna?

Jason Cong, Vaughn Betz, 2013, FPGA '13.

Unified synthesis techniques for high performance fpga designs

Gang Chen, Jason Cong, 2005 .

An Efficient Multilayer MCM Router Based on Four-Via Routing

Jason Cong, Kei-Yong Khoo, J. Cong, 1993, 30th ACM/IEEE Design Automation Conference.

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications

Jason Cong, Mau-Chung Frank Chang, Tatsuo Itoh, 2019, IEEE Journal of Solid-State Circuits.

An energy-efficient adaptive hybrid cache

Jason Cong, Glenn Reinman, Yi Zou, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration

Jason Cong, Hao Wu, Mau-Chung Frank Chang, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness

Jason Cong, Yiyu Shi, Guojie Luo, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On the futility of statistical power optimization

Jason Cong, Puneet Gupta, John Lee, 2009, 2009 Asia and South Pacific Design Automation Conference.

Layout optimization

Jason Cong, Cheng-Kok Koh, Lei He, 1997 .

Computed Tomography Image Enhancement using 3D Convolutional Neural Network pdf

Jason Cong, Wen Gao, Meng Li, 2018, DLMIA/ML-CDS@MICCAI.

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs

Jason Cong, Xin Li, Sheqin Dong, 2008, 2008 Asia and South Pacific Design Automation Conference.

Towards layout-friendly high-level synthesis

Jason Cong, Bin Liu, Guojie Luo, 2012, ISPD '12.

An efficient technique for device and interconnect optimization in deep submicron designs

Jason Cong, Lei He, 1998, ISPD '98.

Edge separability based circuit clustering with application to circuit partitioning

Jason Cong, Sung Kyu Lim, J. Cong, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Accelerator-rich CMPs: From concept to real hardware

Jason Cong, Muhuan Huang, Yu-Ting Chen, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver

Jason Cong, Mau-Chung Frank Chang, Yanghyo Kim, 2013, IEEE Microwave and Wireless Components Letters.

A Provably Good Algorithm for k-Layer Topological Planar Routing Problems

Jason Cong, Moazzem Hossain, Naveed Sherwani, 1993, The Sixth International Conference on VLSI Design.

mPL6: a robust multilevel mixed-size placement engine

Joseph R. Shinnerl, Jason Cong, Min Xie, 2005, ISPD '05.

TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference

Peng Zhang, Jason Cong, Cody Hao Yu, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization

Jason Cong, Xin Yuan, David Z. Pan, 2001 .

Modeling and optimization of vlsi interconnects

Jason Cong, Lei He, 1999 .

Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony

Jason Cong, Hugh T. Blair, Allan Wu, 2014, Philosophical Transactions of the Royal Society B: Biological Sciences.

Automatic design planning and exploration of vlsi systems

Jason Cong, Michail Romesis, 2005 .

A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications

Jason Cong, Adrian Tang, Mau-Chung Frank Chang, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis

Jason Cong, Wei Jiang, Hui Huang, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems

Jason Cong, Yun Liang, Songwu Lu, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA

Jason Cong, Zhiru Zhang, Shih-Chieh Chang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Optimal wiresizing for interconnects with multiple sources

Jason Cong, Lei He, 1995, ICCAD.

Optimality and Stability Study of Timing-Driven Placement Algorithms

Jason Cong, Min Xie, Michail Romesis, 2003, ICCAD 2003.

FPGA Simulation Engine for Customized Construction of Neural Microcircuit

Jason Cong, Hugh T. Blair, Di Wu, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Polyhedral-based data reuse optimization for configurable computing

Jason Cong, Peng Zhang, P. Sadayappan, 2013, FPGA '13.

An Optimal Performance-Driven Technology Mapping Algorithm For Lut-Based Fpgas Under Arbitrary Net-D

Jason Cong, Yuzheng Ding, 1993, ICCAD 1993.

Optimal FPGA mapping and retiming with efficient initial state computation

Jason Cong, Chang Wu, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal simultaneous module and multivoltage assignment for low power

Jason Cong, Deming Chen, Junjuan Xu, 2006, TODE.

Synthesis for FPGAs with embedded memory blocks

Jason Cong, Kenneth Yan, 2000, FPGA '00.

Improving polyhedral code generation for high-level synthesis

Jason Cong, Peng Li, Deming Chen, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Bounded-skew clock and Steiner routing

Jason Cong, Cheng-Kok Koh, Andrew B. Kahng, 1998, TODE.

Combinational logic synthesis for LUT based field programmable gate arrays

Jason Cong, Yuzheng Ding, 1996, TODE.

Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster

Jason Cong, Di Wu, Guangyu Sun, 2016, ISLPED.

Exploiting Computation Reuse for Stencil Accelerators

Jason Cong, Yuze Chi, J. Cong, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Smartphone-Based Indoor Map Construction

Jason Cong, Fan Ye, Guojie Luo, 2018, SpringerBriefs in Computer Science.

Constrained floorplan design for flexible blocks

Jason Cong, C. L. Liu, Sai-keung Dong, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

3D recursive Gaussian IIR on GPU and FPGAs — A case for accelerating bandwidth-bounded applications

Jason Cong, Muhuan Huang, Yi Zou, 2011, 2011 IEEE 9th Symposium on Application Specific Processors (SASP).

Physical synthesis techniques for fpga optimization

Jason Cong, Yizhou Lin, 2006 .

Latte: Locality Aware Transformation for High-Level Synthesis

Jason Cong, Peng Wei, Cody Hao Yu, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

Jason Cong, Yuzheng Ding, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface

Jason Cong, Hao Wu, Mau-Chung Frank Chang, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

Jason Cong, Deming Chen, Yiping Fan, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Automatic memory partitioning and scheduling for throughput and power optimization

Jason Cong, Wei Jiang, Bin Liu, 1999, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Bitwidth-aware scheduling and binding in high-level synthesis

Jason Cong, Zhiru Zhang, Xu Cheng, 2005, ASP-DAC.

An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only)

Jason Cong, Peipei Zhou, Yuze Chi, 2018, FPGA.

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Jason Cong, Zhiru Zhang, Deming Chen, 2016, IET Cyper-Phys. Syst.: Theory & Appl..

LUT-based FPGA technology mapping for reliability

Jason Cong, Kirill Minkovich, 2010, Design Automation Conference.

A Fully Pipelined and Dynamically Composable Architecture of CGRA

Jason Cong, Peipei Zhou, Hui Huang, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

S2FA: An Accelerator Automation Framework for Heterogeneous Computing in Datacenters

Jason Cong, Peng Wei, Cody Hao Yu, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Transformation from ad hoc EDA to algorithmic EDA

Jason Cong, J. Cong, 2012, ISPD '12.

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Jason Cong, Cody Hao Yu, Atefeh Sohrabizadeh, 2020, ACM Trans. Design Autom. Electr. Syst..

Extending High-Level Synthesis for Task-Parallel Programs

Jason Cong, Yuze Chi, Jason Lau, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA

Jason Cong, Licheng Guo, Jie Wang, 2021, FPGA.

SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation pdf

Jason Cong, Yuze Chi, Atefeh Sohrabizadeh, 2021, FPGA.

Pyxis: An Open-Source Performance Dataset of Sparse Accelerators pdf

Jason Cong, Yuze Chi, Linghao Song, 2021, ArXiv.

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Jason Cong, Peng Wei, Ramesh Karri, 2021, 2021 Formal Methods in Computer Aided Design (FMCAD).

Optimal Qubit Mapping with Simultaneous Gate Absorption pdf

Jason Cong, Bochen Tan, J. Cong, 2021, ArXiv.

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication pdf

Jason Cong, Yuze Chi, Atefeh Sohrabizadeh, 2021, FPGA.

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs

Jason Cong, Yuze Chi, Ecenur Ustun, 2021, FPGA.

Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned pdf

Jason Cong, Jie Wang, J. Cong, 2021, ArXiv.

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation

Jason Cong, Liancheng Jia, Jieming Yin, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper

Jason Cong, Bochen Tan, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators

Jason Cong, Peng Wei, Cody Hao Yu, 2021, FPGA.

Extending High-Level Synthesis for Task-Parallel Programs

Jason Cong, Young-kyu Choi, Yuze Chi, 2020, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Optimality Study of Existing Quantum Computing Layout Synthesis Tools

Jason Cong, Bochen Tan, 2021, IEEE Transactions on Computers.

Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication pdf

Jason Cong, Yuze Chi, Licheng Guo, 2021, ArXiv.

Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks pdf

Jason Cong, Yizhou Sun, Atefeh Sohrabizadeh, 2021, ArXiv.

FANS: FPGA-Accelerated Near-Storage Sorting

Jason Cong, Weikang Qiao, Licheng Guo, 2021, 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

HBM Connect: High-Performance HLS Interconnect for FPGA HBM

Jason Cong, Young-kyu Choi, Yuze Chi, 2021, FPGA.

Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope

Jason Cong, Hugh T. Blair, Daniel Aharoni, 2021, 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Quantitative Studies of Impact of 3 D IC Design on Repeater Usage

Jason Cong, Guojie Luo, Chunyue Liu, 2008 .

Thermal-Aware Physical Design Flow for 3-D ICs

Jason Cong, Yan Zhang, 2006 .

Robust Mixed-Size Placement by Recursive Legalized Bipartitioning ⁄

Joseph R. Shinnerl, Jason Cong, Michail Romesis, 2005 .

RASP : A Performance-Driven General Logic Synthesis System for SRAM-based FPGAs

Jason Cong, Songjie Xu, Yuzheng Ding, 1998 .

Impulse response analysis of coherent waveguide communication

Jason Cong, Adrian Tang, Tatsuo Itoh, 2017, International Journal of Microwave and Wireless Technologies.

Matching-Based Methods for High-Performance

Jason Cong, Andrew B. Kahng, Gabriel Robins, 1993 .

3 D Recursive Gaussian IIR on GPUs and FPGAs A Case Study for Accelerating Bandwidth-Bounded Applications

Jason Cong, Muhuan Huang, Yi Zou, 2011 .

Global SPFD Based Rewiring

Jason Cong, Wangning Long, 2000 .

Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization

Jason Cong, David Zhigang Pan, Prasanna V. Srinivas, 2000 .

Convergent Net Weighting Schemes in Hypergraph-based Optimization ∗

Jason Cong, Tony F. Chan, Eric M. Radke, 2009 .

On the Minimum Density Interconnection Tree Problem

Jason Cong, Majid Sarrafzadeh, Andrew B. Kahng, 1994 .

CROSSTALK NOISE CONTROL IN GRIDLESS GENERAL-AREA ROUTING

Jason Cong, Chin-Chih Chang, 1998 .

Fast optimal algorithms for the minimum rectilinear Steiner arborescence problem

Jason Cong, Kwok-Shing Leung, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

AXR-CMP : Architecture Support in Accelerator-Rich CMPs

Jason Cong, Glenn Reinman, Chunyue Liu, 2011 .

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

Jason Cong, Yuzheng Ding, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

An Enhanced Multilevel Algorithm for Circuit Placement

Joseph R. Shinnerl, Jason Cong, Tony F. Chan, 2003, ICCAD 2003.

Multi-way partitioning using bi-partition heuristics

Jason Cong, Majid Sarrafzadeh, Maogang Wang, 2000, ASP-DAC '00.

Logic synthesis for lookup-table based field-programmable gate arrays

Jason Cong, Yean-Yow Hwang, 1999 .

An E cient Approach to Multi-layer Layer Assignment with Application to Via Minimization 1

Jason Cong, Chin-Chih Chang, 1997 .