J. Hein

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Qicheng Yu, B.W. Garlepp, M.H. Perrott, 2006, IEEE Journal of Solid-State Circuits.

A CMOS direct access arrangement using digital capacitive isolation

N. Sooch, J. Scott, J. Hein, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 245 Mb/s EPR4 read/write channel with digital timing recovery

G. Feyh, Q. Li, K. Anderson, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).